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Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
......................................................................
Patch Set 11:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/82682/comment/0054051f_fc106481?us… :
PS11, Line 546: return config->vccin_aux_imon_iccmax ? config->vccin_aux_imon_iccmax : ICC_MAX_ID_ADL_N_MA;
exceed the limit on the length of lines
https://review.coreboot.org/c/coreboot/+/82682/comment/c872bf64_c6f27f69?us… :
PS11, Line 1019: s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax(config) * 4 / MILLIAMPS_TO_AMPS;
exceed the limit on the length of lines
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Change subject: mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/nissa/var/riven: Add G2 touchscreen support
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Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC
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Set Ready For Review
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Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 74:
(3 comments)
Patchset:
PS31:
> > I am working on it. […]
Hi Subrata, we are able get the Google/fatcat recipe working with PTL SOC code in the relation chain.
Patchset:
PS37:
> Sure Subrata.
Acknowledged
Patchset:
PS42:
> Hi Subrata, we are now working with upstream coreboot stage wise CL with below stratgey. […]
Acknowledged
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Change subject: mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`
......................................................................
mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`
Add the support LP5 RAM parts for fatcat:
DRAM Part Name ID to assign
H58G56BK7BX068 0 (0000)
BUG=b:347669091
TEST=emerge-fatcat coreboot
Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
A src/mainboard/google/fatcat/variants/fatcat/memory/Makefile.mk
A src/mainboard/google/fatcat/variants/fatcat/memory/dram_id.generated.txt
A src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt
3 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/83824/1
diff --git a/src/mainboard/google/fatcat/variants/fatcat/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/memory/Makefile.mk
new file mode 100644
index 0000000..efbc56e
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/fatcat/memory src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068
diff --git a/src/mainboard/google/fatcat/variants/fatcat/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/fatcat/memory/dram_id.generated.txt
new file mode 100644
index 0000000..4f615f5
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/fatcat/memory src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+H58G56BK7BX068 0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt
new file mode 100644
index 0000000..17ee7ef
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
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Change subject: util/spd_tools: Add Intel Panther Lake (PTL) platform
......................................................................
Patch Set 1: Code-Review+2
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83823?usp=email
to look at the new patch set (#2).
Change subject: mb/google/nissa/var/riven: Add G2 touchscreen support
......................................................................
mb/google/nissa/var/riven: Add G2 touchscreen support
This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:350844195
TEST=emerge-nissa coreboot
boot with G2 TS, make sure G2 TS is functional.
Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/83823/2
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