Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 74:
(5 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/0a2cca84_bff85cb3?us… :
PS73, Line 45: SOC_INTEL_PANTHERLAKE_U_H
> this is misleading, […]
Hi Subrata,
We have 3 SKUs, U15 (PTL-U 15W Processor Base Power), H25 (PTL-H 12Xe25W Processor Base Power) & H25 (PTL-H 4Xe 25W Processor Base Power).
Please ref doc #823589, section 2.0 table.
As suggested, i will be using two Kconfig SOC_INTEL_PANTHERLAKE_U_H & SOC_INTEL_PANTHERLAKE_H (which only supports PTL H 4Xe)
https://review.coreboot.org/c/coreboot/+/83635/comment/876e8832_9282becf?us… :
PS73, Line 260:
> Can you please add the Pcie ltr max snoop/nosnoop latency values as well? […]
Ack, Adding in ramstage.
https://review.coreboot.org/c/coreboot/+/83635/comment/7d9df8f5_c90919aa?us… :
PS73, Line 269: SOC_INTEL_ACPI_GPIO_PINCTRL_COMPACT
> I thought GPIO CL will introduce this Kconfig ?
Ack, Moved to GPIO CL.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/16559b66_71f3ded1?us… :
PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */
: enum lpm_state_mask {
: LPM_S0i2_0 = BIT(0),
: LPM_S0i2_1 = BIT(1),
: LPM_S0i2_2 = BIT(2),
: LPM_S0i3_0 = BIT(3),
: LPM_S0i3_1 = BIT(4),
: LPM_S0i3_2 = BIT(5),
: LPM_S0i3_3 = BIT(6),
: LPM_S0i3_4 = BIT(7),
: LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
: | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
: };
:
> > Hi Subrata, we will be using these macros to get supported lpm mask. […]
Ack, moving to ramstage.
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/7e46a5ff_d9362283?us… :
PS72, Line 5: PTL_U_H_POWER_LIMITS
> > Hi Subrata, i have added the corresponding 15W/25W/45W into enum. […]
Hi Subrata, we referred the data from FSP, due to PDG guide requires PNP completion, which is not achieved yet. Its too early. Anyway, i will keep a note in crosbug to update the data from PDG doc.
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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#24).
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/me.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
M src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/me.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
40 files changed, 3,711 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/24
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,130 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/74
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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/systemagent_early.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_gpmr.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
73 files changed, 5,868 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/13
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Change subject: soc/intel/common/systemagent: Improve systemagent
......................................................................
soc/intel/common/systemagent: Improve systemagent
System agent in Intel common block (1) assumes TOLUD and TOUUD
registers hold the max available address plus 1, but on some SoC like
Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD
and TSEG registers to 1 MiB default, but some SoC may have different
alignments. This patch add a new weak function
`soc_systemagent_fixup_address()` to improve it.
CAPID_A, BDSM and BGSM registers may not exist on specific platform,
this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER`
to select them.
Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
5 files changed, 56 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/12
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Change subject: drivers/soundwire: Support Realtek ALC722 codec
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Patch Set 9: Code-Review+2
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Morris Hsu has posted comments on this change by Morris Hsu. ( https://review.coreboot.org/c/coreboot/+/83874?usp=email )
Change subject: mb/google/brox/jubilant: Disable devcies and GPIOs by fw_config
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/brox/variants/jubilant/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83874/comment/8cb73332_a08febff?us… :
PS7, Line 3: STORAGE_UNKNOWN
> It should be STORAGE_UNPROVISIONED and its value/mask should be 3.
done.
https://review.coreboot.org/c/coreboot/+/83874/comment/d165e197_21245cfb?us… :
PS7, Line 297: STORAGE_UNKNOWN
> I think it should be STORAGE_UNPROVISIONED. An unprovisioned FW_CONFIG should be 0xffffffff. […]
done.
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