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Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/83946/comment/258dc692_3031ec0d?us… :
PS4, Line 498: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE
> As I learned from the Intel cache team during another hang issue in Ovis with 18MB of cache, when we […]
I am limiting the Way Size to the Effective Way Size allowing me to compute the Max NEM Size. On a SKU with the following LLC.
Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 24576
Cache size = 18 MiB
I get a way size of 1 \* 64 \* 24576 = 1572864 = 0x1800000.
Then an effective way size of 0x100000
leading to a NEM size of 12 MB which is aligned with MTL HAS or Alder Lake EDS.
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Change subject: soc/intel/common/block/cpu: Fix number of way computation
......................................................................
soc/intel/common/block/cpu: Fix number of way computation
The way size is not necessarily a power of two. As a result, dividing
`CONFIG_DCACHE_RAM_SIZE' by the way size can leave a remainder. That
remainder should be taken into account to compute the number of way.
BUG=b:360332771
TEST=Verified on rex
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/83982/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index f412cc5..109b3f6 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -512,6 +512,11 @@
mov $CONFIG_DCACHE_RAM_SIZE, %eax
xor %edx, %edx
div %ecx
+ /* Take the remainder into account */
+ movl $0x01, %ecx
+ cmp $0x00, %edx
+ cmovne %ecx, %edx
+ add %edx, %eax
mov %eax, %edx /* back up data_ways in edx */
mov %eax, %ecx
movl $0x01, %eax
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Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and vw mapping fix
......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID and vw mapping fix
Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
Change cpu_port field to 16-bit width if the Kconfig is set.
Support GPIO group for the virtual wire mapping whose bit position
starts with non-zeo.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
3 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/2
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
......................................................................
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
---
M src/soc/intel/alderlake/include/soc/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/meteorlake/include/soc/tcss.h
M src/soc/intel/tigerlake/include/soc/tcss.h
4 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83980/3
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
......................................................................
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
---
M src/soc/intel/alderlake/include/soc/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/meteorlake/include/soc/tcss.h
M src/soc/intel/tigerlake/include/soc/tcss.h
4 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83980/2
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Change subject: util/cbfstool/cbfs-payload-linux: Add error handling
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/066ec36c_7213bcb6?us… :
PS17, Line 54: .port = PID_GPIOCOM0,
> Subrata, okay. I will submit two patches. […]
Subrata, I have added these two CLs:
soc/intel/common/gpio: support 16-bit CPU Port ID and virtual wire mapping fix
https://review.coreboot.org/c/coreboot/+/83981
soc/intel/common/tcss: Move AUX bias ctrl register field defines to TCSS SOC header
https://review.coreboot.org/c/coreboot/+/83980
Saurabh and I will rebase to these and make the changes according to these:
- Add new Kconfig flag
- PTL SOC GPIO to add 16-bit PID for cpu_port and virtual mapping, and tcss AUX bias ctrl register field defines.
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Change subject: arch/x86/boot: Jump to payload in protected mode
......................................................................
Patch Set 34:
(1 comment)
File src/include/assert.h:
https://review.coreboot.org/c/coreboot/+/30118/comment/0573b1ac_587613e9?us… :
PS34, Line 87: (uint32_t)(uintptr_t)(x); \
> this line is unreachable, or I'm wrong?
That line is reached when x points at the lower 4GB.
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Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and virtual wire mapping fix
......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID and virtual wire mapping fix
Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
Change cpu_port field to 16-bit width if the Kconfig is set.
Support GPIO group for the virtual wire mapping whose bit position
starts with non-zeo.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
3 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig
index de0546c..0dcc61e 100644
--- a/src/soc/intel/common/block/gpio/Kconfig
+++ b/src/soc/intel/common/block/gpio/Kconfig
@@ -63,4 +63,10 @@
SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser
is 4 bits to support Native Function 1 to 15.
+config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID
+ bool
+ default n
+ help
+ Use 16-bit CPU port ID.
+
endif
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index d49742d..2d3f800 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -1070,7 +1070,10 @@
offset += pad - comm->vw_entries[i].first_pad;
*vw_index = comm->vw_base + offset / 8;
- *vw_bit = offset % 8;
+ if (comm->vw_bit_start_pos)
+ *vw_bit = (offset + comm->vw_bit_start_pos[i]) % 8;
+ else
+ *vw_bit = offset % 8;
return true;
}
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 8e60a16..fe455db 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -136,7 +136,11 @@
uint8_t gpi_status_offset; /* specifies offset in struct
gpi_status */
uint8_t port; /* PCR Port ID */
- uint8_t cpu_port; /* CPU Port ID */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID)
+ uint16_t cpu_port; /* Use 16-bit CPU Port ID */
+#else
+ uint8_t cpu_port; /* Use 8-bit CPU Port ID */
+#endif
const struct reset_mapping *reset_map; /* PADRSTCFG logical to
chipset mapping */
size_t num_reset_vals;
@@ -148,6 +152,7 @@
* which they map to VW indexes (beginning with VW base)
*/
const struct vw_entries *vw_entries;
+ const uint8_t *vw_bit_start_pos;
size_t num_vw_entries;
};
--
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Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Gerrit-Change-Number: 83981
Gerrit-PatchSet: 1
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>