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Change subject: soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA
......................................................................
Patch Set 10:
(1 comment)
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/984e85cd_5ae62fbf?us… :
PS10, Line 11: FULLnHALF
UPPER_CASE please.
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Change subject: soc/mediatek: Refactor MMU operation for L2C SRAM and DMA
......................................................................
Patch Set 7: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 7: -Code-Review
(1 comment)
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/83923/comment/141d67b3_30772206?us… :
PS5, Line 33: void mtk_snfc_init(void)
: {
: const struct pad_func *ptr;
:
: for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) {
: ptr = &nor_pinmux[i];
:
: gpio_set_pull(ptr->gpio, GPIO_PULL_ENABLE, ptr->select);
: gpio_set_mode(ptr->gpio, ptr->func);
:
: if (gpio_set_driving(ptr->gpio, GPIO_DRV_14_MA) < 0)
: printk(BIOS_ERR,
: "%s: failed to set pin drive to 14 mA for %d\n",
: __func__, ptr->gpio.id);
: else
: printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__,
: gpio_get_driving(ptr->gpio));
: }
: }
> 1. It would be nice to make them as similar as possible. […]
I agree that part of the code (and the `pad_func` struct) can be moved to the common code (but of course after `gpio_t` is moved to common code, as suggested in CB:83922), so that it could be shared among mt8186, mt8188 and mt8196. How about we add
```
// Whatever name you prefer
void mtk_snfc_init_pad_func(const struct pad_func *pad_func);
```
to the common code, and then here the code can be simplified:
```
void mtk_snfc_init(void)
{
for (...)
mtk_snfc_init_pad_func(&nor_pinmux[i]);
}
```
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Change subject: mb/goog/brya: unlock gpio wake sources
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Patch Set 8: Code-Review+2
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Change subject: Docs: Fix broken header references
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83976/comment/1d675425_8c79fb82?us… :
PS1, Line 10: lower-case
> I think this is called `slug-case`
Done
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Change subject: soc/mediatek/mt8196: Add GPIO driver
......................................................................
Patch Set 6:
(1 comment)
File src/soc/mediatek/mt8196/include/soc/gpio_base.h:
PS4:
> This .h file is included by common/soc, but 8173 uses a different gpio_base from the others. […]
MT8173 has an even simpler definition:
```
typedef struct {
u32 id;
} gpio_t;
```
The maximum ID for MT8173 is 134, so 8 bits should be enough for the `id` field. That means MT8173 can use this shared `gpio_t` as well. It just doesn't use the other fields.
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83984?usp=email )
Change subject: mb/google/brox: Enable storage devices on unprovisioned fw_config
......................................................................
mb/google/brox: Enable storage devices on unprovisioned fw_config
Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83984/1
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 21774f8..18baa5d 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -290,6 +290,7 @@
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
probe STORAGE STORAGE_NVME
+ probe unprovisioned
end
device ref pcie_rp5 on
register "pch_pcie_rp[PCH_RP(5)]" = "{
@@ -327,9 +328,11 @@
end
probe ISH ISH_ENABLE
probe STORAGE STORAGE_UFS
+ probe unprovisioned
end
device ref ufs on
probe STORAGE STORAGE_UFS
+ probe unprovisioned
end
end
end
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