coreboot-gerrit August 2024

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[M] Change in coreboot[main]: region: Turn region_end() into an inclusive region_last()
by Julius Werner (Code Review) 23 Aug '24

23 Aug '24

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79946?usp=email ) Change subject: region: Turn region_end() into an inclusive region_last() ...................................................................... region: Turn region_end() into an inclusive region_last() The current region_end() implementation is susceptible to overflow if the region is at the end of the addressable space. A common case with the memory-mapped flash of x86 directly below the 32-bit limit. Note: This patch also changes console output to inclusive limits. IMO, to the better. Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/spi/winbond.c M tests/commonlib/region-test.c M tests/lib/region_file-test.c M util/cbfstool/cbfstool.c M util/cbfstool/cse_serger.c 8 files changed, 23 insertions(+), 27 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 8471797..e066ea0 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -124,15 +124,15 @@ return r->size; } -static inline size_t region_end(const struct region *r) +static inline size_t region_last(const struct region *r) { - return region_offset(r) + region_sz(r); + return region_offset(r) + (region_sz(r) - 1); } static inline bool region_overlap(const struct region *r1, const struct region *r2) { - return (region_end(r1) > region_offset(r2)) && - (region_offset(r1) < region_end(r2)); + return (region_last(r1) >= region_offset(r2)) && + (region_offset(r1) <= region_last(r2)); } /* Helper to dynamically initialize region device. */ @@ -156,9 +156,9 @@ return region_offset(region_device_region(rdev)); } -static inline size_t region_device_end(const struct region_device *rdev) +static inline size_t region_device_last(const struct region_device *rdev) { - return region_end(region_device_region(rdev)); + return region_last(region_device_region(rdev)); } /* Memory map entire region device. Same semantics as rdev_mmap() above. */ diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4153f0a..fbc6276 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -10,10 +10,10 @@ if (region_offset(c) < region_offset(p)) return 0; - if (region_end(c) > region_end(p)) + if (region_last(c) > region_last(p)) return 0; - if (region_end(c) < region_offset(c)) + if (region_last(c) < region_offset(c)) return 0; return 1; diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 979fa48..c6d0753 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -341,7 +341,7 @@ } for (int i = 0; i < loader_params->num_cpus; i++) - mod_params->save_state_top[i] = region_end(&cpus[i].ss); + mod_params->save_state_top[i] = region_last(&cpus[i].ss) + 1; if (CONFIG(RUNTIME_CONFIGURABLE_SMM_LOGLEVEL)) mod_params->smm_log_level = mainboard_set_smm_log_level(); @@ -371,7 +371,7 @@ static void print_region(const char *name, const struct region region) { printk(BIOS_DEBUG, "%-12s [0x%zx-0x%zx]\n", name, region_offset(&region), - region_end(&region)); + region_last(&region)); } /* STM + Handler + (Stub + Save state) * CONFIG_MAX_CPUS + stacks + page tables*/ @@ -482,7 +482,7 @@ return -1; const struct region smram = region_create(smram_base, smram_size); - const uintptr_t smram_top = region_end(&smram); + const uintptr_t smram_top = region_last(&smram) + 1; const size_t stm_size = CONFIG(STM) ? CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE : 0; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 3426d08..db93ff6 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -374,7 +374,7 @@ } printk(BIOS_DEBUG, "WINBOND: flash protected range 0x%08zx-0x%08zx\n", - region_offset(&wp_region), region_end(&wp_region)); + region_offset(&wp_region), region_last(&wp_region)); return region_is_subregion(&wp_region, region); } @@ -502,7 +502,7 @@ int ret; /* Need to touch TOP or BOTTOM */ - if (region_offset(region) != 0 && region_end(region) != flash->size) + if (region_offset(region) != 0 && region_last(region) != flash->size - 1) return -1; params = flash->part; @@ -600,7 +600,7 @@ return ret; printk(BIOS_DEBUG, "WINBOND: write-protection set to range " - "0x%08zx-0x%08zx\n", region_offset(region), region_end(region)); + "0x%08zx-0x%08zx\n", region_offset(region), region_last(region)); return ret; } diff --git a/tests/commonlib/region-test.c b/tests/commonlib/region-test.c index 3280482..6caa12c 100644 --- a/tests/commonlib/region-test.c +++ b/tests/commonlib/region-test.c @@ -17,7 +17,7 @@ struct region outer = {.offset = VAL(2), .size = VAL(4)}; assert_int_equal(region_offset(&outer), VAL(2)); assert_int_equal(region_sz(&outer), VAL(4)); - assert_int_equal(region_end(&outer), VAL(6)); + assert_int_equal(region_last(&outer), VAL(6) - 1); struct region inner = {.offset = VAL(3), .size = VAL(2)}; assert_true(region_is_subregion(&outer, &inner)); @@ -118,7 +118,7 @@ { assert_int_equal(region_device_offset(&mock_rdev), 0); assert_int_equal(region_device_sz(&mock_rdev), ~(size_t)0); - assert_int_equal(region_device_end(&mock_rdev), ~(size_t)0); + assert_int_equal(region_device_last(&mock_rdev), ~(size_t)0 - 1); } /* @@ -254,7 +254,7 @@ assert_int_equal(rdev_chain(&child, &mock_rdev, child_offs, child_size), 0); assert_int_equal(region_device_sz(&child), child_size); assert_int_equal(region_device_offset(&child), child_offs); - assert_int_equal(region_device_end(&child), child_offs + child_size); + assert_int_equal(region_device_last(&child), child_offs + child_size - 1); assert_int_equal(rdev_relative_offset(&mock_rdev, &child), child_offs); assert_int_equal(rdev_relative_offset(&child, &mock_rdev), -1); diff --git a/tests/lib/region_file-test.c b/tests/lib/region_file-test.c index 56bb8e4f..7607aaf 100644 --- a/tests/lib/region_file-test.c +++ b/tests/lib/region_file-test.c @@ -145,12 +145,8 @@ static void test_region_file_init_invalid_region_device(void **state) { struct region_device bad_dev; - struct region_file regf; - rdev_chain_mem_rw(&bad_dev, NULL, 0); - - /* Expect fail when passing invalid region_device. */ - assert_int_equal(-1, region_file_init(&regf, &bad_dev)); + assert_int_equal(rdev_chain_mem_rw(&bad_dev, NULL, 0), -1); } static void test_region_file_data(void **state) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index cc8dbb5..25f4847 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -423,9 +423,9 @@ &mmap_window_table[j].flash_space)) { ERROR("Flash space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", region_offset(&mmap_window_table[i].flash_space), - region_end(&mmap_window_table[i].flash_space), + region_last(&mmap_window_table[i].flash_space), region_offset(&mmap_window_table[j].flash_space), - region_end(&mmap_window_table[j].flash_space)); + region_last(&mmap_window_table[j].flash_space)); return false; } @@ -433,9 +433,9 @@ &mmap_window_table[j].host_space)) { ERROR("Host space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", region_offset(&mmap_window_table[i].flash_space), - region_end(&mmap_window_table[i].flash_space), + region_last(&mmap_window_table[i].flash_space), region_offset(&mmap_window_table[j].flash_space), - region_end(&mmap_window_table[j].flash_space)); + region_last(&mmap_window_table[j].flash_space)); return false; } } diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index 006a01e..9d74a12 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -647,7 +647,7 @@ size_t end_offset; for (size_t i = 0; i < BP_TOTAL; i++) { - end_offset = region_end(&params.layout_regions[i]); + end_offset = region_last(&params.layout_regions[i]) + 1; if (end_offset > offset) offset = end_offset; } -- To view, visit https://review.coreboot.org/c/coreboot/+/79946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Gerrit-Change-Number: 79946 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: region: Turn region_end() into an inclusive region_last()
by Julius Werner (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Jakub Czapiga, Jérémy Compostella, Nico Huber, Werner Zeh. Julius Werner has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79946?usp=email ) Change subject: region: Turn region_end() into an inclusive region_last() ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/commonlib/region.c: https://review.coreboot.org/c/coreboot/+/79946/comment/c671fbb4_083abe57?us… : PS5, Line 16: if (region_last(c) < region_offset(p)) > Looks like this is done. Please re-open if I missed anything. I think what I meant here was to remove the `region_last(c) < region_offset(c)` check, because your `region_create()` stuff already guarantees that regions can't wrap around. Although on closer inspection, I think that's not quite true yet: `rdev_readat()` still creates a `struct region` by hand and can sometimes be called with untrusted inputs. Let's merge this for now because that isn't quite related to the point of this patch. But it would be good (if you have time) to also make the code inside `region.c` itself use the `region_create()` APIs where necessary to guarantee that we really won't have any wraparounds, and then you can remove that check in `region_is_subregion()`. -- To view, visit https://review.coreboot.org/c/coreboot/+/79946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Gerrit-Change-Number: 79946 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 23 Aug 2024 01:08:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: coreboot org <coreboot.org(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: WIP: Update VBOOT for AR fixes for LLD
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84050?usp=email ) Change subject: WIP: Update VBOOT for AR fixes for LLD ...................................................................... WIP: Update VBOOT for AR fixes for LLD Change-Id: Idf2bc8f4bcdf59691c0f0a4c4d5b33fe56dc8ad6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/84050/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index f1f70f4..85c6bae 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2 +Subproject commit 85c6bae530e4326b172fbf0ff12471716ff5ed2e -- To view, visit https://review.coreboot.org/c/coreboot/+/84050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf2bc8f4bcdf59691c0f0a4c4d5b33fe56dc8ad6 Gerrit-Change-Number: 84050 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: soc/intel/apl: Fix building with clang & LTO
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Sean Rhodes. Hello Sean Rhodes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84047?usp=email to look at the new patch set (#3). Change subject: soc/intel/apl: Fix building with clang & LTO ...................................................................... soc/intel/apl: Fix building with clang & LTO With LTO enabled assigning a void * to an UINT32 gets a warning so cast explicitly. Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84047/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Gerrit-Change-Number: 84047 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: arch/x86/Kconfig: Fix linking with LLD
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84049?usp=email ) Change subject: arch/x86/Kconfig: Fix linking with LLD ...................................................................... arch/x86/Kconfig: Fix linking with LLD Somehow the trick for older binutils is also needed for LLD. Change-Id: I1a6a5ef9dc6d824fa108681689a69df3faefd3c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84049/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 16d8a70..64d69ef 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -413,6 +413,7 @@ config X86_BOOTBLOCK_EXTRA_PROGRAM_SZ int + default 4196 if LTO && COMPILER_LLVM_CLANG default 1024 if CHROMEOS default 0 help -- To view, visit https://review.coreboot.org/c/coreboot/+/84049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a6a5ef9dc6d824fa108681689a69df3faefd3c6 Gerrit-Change-Number: 84049 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: arch/x86/car.ld: Fix overlapping regions
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84048?usp=email ) Change subject: arch/x86/car.ld: Fix overlapping regions ...................................................................... arch/x86/car.ld: Fix overlapping regions Make sure .car.data and .car.fspm_rc_heap don't overlap. Clang with LLD does not like this. Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/84048/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index f99304f..4c869df 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -5,10 +5,9 @@ #include <memlayout.h> /* This file is included inside a SECTIONS block */ -. = CONFIG_DCACHE_RAM_BASE; +. = CONFIG_DCACHE_RAM_BASE + CONFIG_FSP_M_RC_HEAP_SIZE; .car.data . (NOLOAD) : { _car_region_start = . ; - . += CONFIG_FSP_M_RC_HEAP_SIZE; #if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND) REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16) #endif @@ -113,8 +112,7 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) - CONFIG_FSP_T_RESERVED_SIZE; -. = _car_region_start; -.car.fspm_rc_heap . (NOLOAD) : { +.car.fspm_rc_heap (CONFIG_DCACHE_RAM_BASE) (NOLOAD) : { . += CONFIG_FSP_M_RC_HEAP_SIZE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Gerrit-Change-Number: 84048 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/apl: Fix building with clang & LTO
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Sean Rhodes. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84047?usp=email ) Change subject: soc/intel/apl: Fix building with clang & LTO ...................................................................... soc/intel/apl: Fix building with clang & LTO With LTO enabled assigning a void * to an UINT32 gets a warning so cast explicitly. Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/84047/1 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f710883..4a3cf94 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -316,7 +316,7 @@ */ mupd->FspmConfig.VariableNvsBufferPtr = - mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, + (UINT32)mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, NULL); assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); -- To view, visit https://review.coreboot.org/c/coreboot/+/84047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Gerrit-Change-Number: 84047 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: Add initial experimental LTO support
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Arthur Heymans, Marvin Drees, Nico Huber, Patrick Rudolph. Hello Marvin Drees, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84003?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Add initial experimental LTO support ...................................................................... Add initial experimental LTO support This will not succeed in compiling on all target and compiler combinations but at least gets the ball rolling. The change is not invasive. Some notes: - GCC has issues with LTO on ARM - Clang uses LLD automatically on some arch - Clang with LTO fails on x86 as it forwards the linking to GCC for some reason - SMM building succeeds but the binary is empty Change-Id: Ieb9204777fd349542744a8946e2207731c37969c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk M src/Kconfig 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84003/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb9204777fd349542744a8946e2207731c37969c Gerrit-Change-Number: 84003 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com>

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[XS] Change in coreboot[main]: arch/arm: Fix building with LTO
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Attention is currently required from: Arthur Heymans, Julius Werner, Nico Huber. Hello Julius Werner, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84005?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: arch/arm: Fix building with LTO ...................................................................... arch/arm: Fix building with LTO With LTO clang cannot find the aliased symbols. Change-Id: I3d89c093cee2636e648987a06afb0d325b1d96ff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/Makefile.mk 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84005/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d89c093cee2636e648987a06afb0d325b1d96ff Gerrit-Change-Number: 84005 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: lib/rmodules: Add support for LTO
by Arthur Heymans (Code Review) 23 Aug '24

23 Aug '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84038?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib/rmodules: Add support for LTO ...................................................................... lib/rmodules: Add support for LTO Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/Makefile.mk 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/84038/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Gerrit-Change-Number: 84038 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2024