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Change subject: mb/lenovo/thinkcentre_m710s: Drop PCH UPDs from PEG device
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Oops, yeah, I had my SSDs mixed up. […]
thanks for verifying that this won't break things
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84077?usp=email )
Change subject: soc/amd/stoneyridge/smihandler: add PSP SMI handler
......................................................................
soc/amd/stoneyridge/smihandler: add PSP SMI handler
Now that the PSP SMI handler for flash access is also implemented for
the PSP generation 1, the PSP SMI handler can be added to the
Stoneyridge code too. The actual PSP SMI handler code will only be added
to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't
the default case, so this patch doesn't change the current behavior
unless that option is also selected. This SMI handler mainly added for
completeness since the PSP firmware blobs released for Stoneyridge are
probably lacking the corresponding PSP-side code to send the PSP SMI to
the host. At least if I remember correctly the PSP bootloader release
for Stoneyridge has the ability to load the secure OS removed and since
the secure OS is the runtime component, some part of that is probably
what's sending those SMIs to the host. If there are some other PSP
bootloader builds that support loading the secure OS, this patch might
still be useful for those.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1
---
M src/soc/amd/stoneyridge/smihandler.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84077/1
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index f962fa0..826dc2a 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -3,6 +3,7 @@
#include <acpi/acpi.h>
#include <amdblocks/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/psp.h>
#include <amdblocks/smi.h>
#include <amdblocks/smm.h>
#include <arch/hlt.h>
@@ -136,6 +137,7 @@
static const struct smi_sources_t smi_sources[] = {
{ .type = SMITYPE_SMI_CMD_PORT, .handler = stoneyridge_fch_apmc_smi_handler },
{ .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler},
+ { .type = SMITYPE_PSP, .handler = psp_smi_handler },
};
void *get_smi_source_handler(int source)
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Verified+1 by build bot (Jenkins)
Change subject: soc/amd/common/psp/psp_smi_flash: introduce common data structures
......................................................................
soc/amd/common/psp/psp_smi_flash: introduce common data structures
The request buffer data structures differ between the PSP generation 1
and 2 in the way that the generation 2 added the 64 bit target NV ID
field right at the beginning of the request buffer data structures. In
order to make the data structure definitions common, remove the
target_nv_id struct element via the preprocessor in case the
SOC_AMD_COMMON_BLOCK_PSP_GEN2 option isn't selected. Since the request
buffer data structures are now common for both generations, also remove
the 'v2' from the struct names.
Document #54267 revision 1.06 was used as reference for the 1st PSP
generation and document #55758 revision 2.04 was used for the 2nd PSP
generation.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
M src/soc/amd/common/block/psp/psp_smi_flash.h
M src/soc/amd/common/block/psp/psp_smi_flash_gen2.c
3 files changed, 40 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/84063/2
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Hello Fred Reitberger, Jason Glenesk, Matt DeVillier,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/psp/psp_smi_flash: implement generation 1 support
......................................................................
soc/amd/common/psp/psp_smi_flash: implement generation 1 support
Implement the request buffer access functions for the PSP generation 1
case. In this case, only the SMI_TARGET_NVRAM is supported, so always
return this target NV ID and always return true in the validity checks
which in the PSP generation 2 case check if the target NV ID is valid.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7e141f846e930bab6972a281745c0180ac52c291
---
M src/soc/amd/common/block/psp/Makefile.mk
A src/soc/amd/common/block/psp/psp_smi_flash_gen1.c
2 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84064/2
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Change subject: Doc/releases: List toolchain updates in coreboot-24.11-relnotes
......................................................................
Doc/releases: List toolchain updates in coreboot-24.11-relnotes
Report upgraded version of binutils, GGC, CMake and LLVM.
Change-Id: I3690882a742cfe1800f20fdf23a836cb297bbe35
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Documentation/releases/coreboot-24.11-relnotes.md
1 file changed, 4 insertions(+), 0 deletions(-)
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Change subject: xcompile: Use Walloc-size GCC option
......................................................................
xcompile: Use Walloc-size GCC option
Change-Id: Ia26dcf0 reverted use of Walloc-size as old GCC didn't
support it. So enable it for modern GCC version.
Change-Id: If5d36b073bb5b4cccb0cf2b67b43edb3f97f168c
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/xcompile/xcompile
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84074/2
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Change subject: mb/*/*/early_init.c: Remove unused included southbridge
......................................................................
Patch Set 1: Code-Review+2
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