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Change subject: cfl/cml/whl mainboards: Drop superfluous cpu_cluster device
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/amd/common/psp_gen2: return status from soc_read_c2p38
......................................................................
soc/amd/common/psp_gen2: return status from soc_read_c2p38
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
---
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
M src/soc/amd/common/block/psp/spl_fuse.c
4 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83447/3
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Change subject: soc/amd: add SoC-specific root_complex.c to SMM
......................................................................
soc/amd: add SoC-specific root_complex.c to SMM
The PSP code introduced in a following patch needs both SoC-specific
functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be
available in SMM, so add those compilation units to the corresponding
target.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8
---
M src/soc/amd/cezanne/Makefile.mk
M src/soc/amd/genoa_poc/Makefile.mk
M src/soc/amd/glinda/Makefile.mk
M src/soc/amd/mendocino/Makefile.mk
M src/soc/amd/phoenix/Makefile.mk
M src/soc/amd/picasso/Makefile.mk
6 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/83445/2
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Change subject: soc/amd/common/block/psp_gen2: add get_psp_mmio_base
......................................................................
soc/amd/common/block/psp_gen2: add get_psp_mmio_base
Add get_psp_mmio_base which reads the PSP MMIO base address from the
hardware registers. Since this function will not only be called in
ramstage, but also in SMM, we can't just look for the specific domain
resource consumer like it is done for the IOAPICs in the northbridge,
but have to get this base address from the registers. In order to limit
the performance impact of this, the base address gets cached in a static
variable if the hardware lock bit of the corresponding base address
register is already set which means the base address can't change any
more before the next reset.
This is a preparation to move back to using MMIO access to the PSP
registers and will also enable cases that require the use of the MMIO
mapping of the PSP registers.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a
---
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
2 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83446/2
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Change subject: soc/amd/common/psp_gen2: return status from soc_read_c2p38
......................................................................
soc/amd/common/psp_gen2: return status from soc_read_c2p38
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
---
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
M src/soc/amd/common/block/psp/spl_fuse.c
4 files changed, 16 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83447/2
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Change subject: mb/google/dedede/var/awasuki: Generate 3 RAM IDs
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83427/comment/9aa954ab_dfe7a18c?us… :
PS3, Line 7: variants
> var
Done
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Change subject: mb/google/dedede/var/awasuki: Generate 3 RAM IDs
......................................................................
mb/google/dedede/var/awasuki: Generate 3 RAM IDs
Vendor DRAM Part Name Type
SAMSUNG K4U6E3S4AB-MGCL LP4X
SAMSUNG K4UBE3D4AB-MGCL LP4X
MICRON MT53E1G32D2NP-046 WT:B LP4X
BUG=b:351968527
TEST=Run part_id_gen tool without any errors
Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f
Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
M src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
3 files changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83427/4
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83448?usp=email )
Change subject: soc/amd/common/psp_gen2: use MMIO access again
......................................................................
soc/amd/common/psp_gen2: use MMIO access again
Now that we have a get_psp_mmio_base function that will work on all SoCs
that use the psp_gen2 code, we can move back to accessing the PSP
registers via their MMIO mapping. This sort-of reverts
commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access
to PSP").
Since the fist get_psp_mmio_base call in SMM will be done in ramstage
when coreboot triggers the APM_CNT_SMMINFO SMI which results in
psp_notify_smm being called, the PSP MMIO base address will already be
saved to the static variable inside get_psp_mmio_base, so we don't have
to worry about get_psp_mmio_base potentially clobbering the SMN index
register during OS runtime. Right now, this doesn't matter, since the
only PSP mailbox command from the SMI handler after coreboot is done and
the OS has taken over will be during the S3/S4/S5 entry which will be
triggered by the OS as last step after is done with all its preparations
for suspend/shutdown. There will however be future patches that add SMI-
handlers that can send PSP mailbox commands during OS runtime where we
have to make sure to not clobber the SMN index register.
TEST=PSP mailbox commands are still sent correctly on Mandolin.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c
---
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_gen2.c
2 files changed, 43 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83448/1
diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c
index a537bff..4ac7aaf 100644
--- a/src/soc/amd/common/block/psp/psb.c
+++ b/src/soc/amd/common/block/psp/psb.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/reset.h>
-#include <amdblocks/smn.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/mmio.h>
@@ -83,9 +82,16 @@
}
}
-static uint32_t get_psb_status(void)
+static enum cb_err get_psb_status(uint32_t *psb_status_value)
{
- return smn_read32(SMN_PSP_PUBLIC_BASE + PSB_STATUS_OFFSET);
+ const uintptr_t psp_mmio = get_psp_mmio_base();
+
+ if (!psp_mmio) {
+ printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n");
+ return CB_ERR;
+ }
+ *psb_status_value = read32p(psp_mmio | PSB_STATUS_OFFSET);
+ return CB_SUCCESS;
}
/*
@@ -102,7 +108,11 @@
}
};
- status = get_psb_status();
+ if (get_psb_status(&status) != CB_SUCCESS) {
+ printk(BIOS_ERR, "PSP: Failed to get base address.\n");
+ return CB_ERR;
+ }
+
printk(BIOS_INFO, "PSB: Status = %x\n", status);
if (status & FUSE_PLATFORM_SECURE_BOOT_EN) {
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 98136d1..dd3e7d3 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -5,11 +5,11 @@
#include <amdblocks/psp.h>
#include <amdblocks/root_complex.h>
#include <amdblocks/smn.h>
+#include <device/mmio.h>
#include "psp_def.h"
#define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */
-#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */
-#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */
+#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */
#define IOHC_MISC_PSP_MMIO_REG 0x2e0
@@ -85,40 +85,37 @@
} __packed fields;
};
-static u16 rd_mbox_sts(void)
+static u16 rd_mbox_sts(uintptr_t psp_mmio)
{
union pspv2_mbox_command tmp;
- tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
+ tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET);
return tmp.fields.mbox_status;
}
-static void wr_mbox_cmd(u8 cmd)
+static void wr_mbox_cmd(uintptr_t psp_mmio, u8 cmd)
{
union pspv2_mbox_command tmp = { .val = 0 };
/* Write entire 32-bit area to begin command execution */
tmp.fields.mbox_command = cmd;
- smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET, tmp.val);
+ write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val);
}
-static u8 rd_mbox_recovery(void)
+static u8 rd_mbox_recovery(uintptr_t psp_mmio)
{
union pspv2_mbox_command tmp;
- tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
+ tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET);
return !!tmp.fields.recovery;
}
-static void wr_mbox_buffer_ptr(void *buffer)
+static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer)
{
- const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32;
- const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff;
- smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h);
- smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l);
+ write64p(psp_mmio | PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer);
}
-static int wait_command(bool wait_for_ready)
+static int wait_command(uintptr_t psp_mmio, bool wait_for_ready)
{
union pspv2_mbox_command and_mask = { .val = ~0 };
union pspv2_mbox_command expected = { .val = 0 };
@@ -136,7 +133,7 @@
stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT);
do {
- tmp = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET);
+ tmp = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET);
tmp &= ~and_mask.val;
if (tmp == expected.val)
return 0;
@@ -147,23 +144,27 @@
int send_psp_command(u32 command, void *buffer)
{
- if (rd_mbox_recovery())
+ const uintptr_t psp_mmio = get_psp_mmio_base();
+ if (!psp_mmio)
+ return -PSPSTS_NOBASE;
+
+ if (rd_mbox_recovery(psp_mmio))
return -PSPSTS_RECOVERY;
- if (wait_command(true))
+ if (wait_command(psp_mmio, true))
return -PSPSTS_CMD_TIMEOUT;
/* set address of command-response buffer and write command register */
- wr_mbox_buffer_ptr(buffer);
- wr_mbox_cmd(command);
+ wr_mbox_buffer_ptr(psp_mmio, buffer);
+ wr_mbox_cmd(psp_mmio, command);
/* PSP clears command register when complete. All commands except
* SxInfo set the Ready bit. */
- if (wait_command(command != MBOX_BIOS_CMD_SX_INFO))
+ if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO))
return -PSPSTS_CMD_TIMEOUT;
/* check delivery status */
- if (rd_mbox_sts())
+ if (rd_mbox_sts(psp_mmio))
return -PSPSTS_SEND_ERROR;
return 0;
@@ -171,6 +172,12 @@
enum cb_err soc_read_c2p38(uint32_t *msg_38_value)
{
- *msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
+ const uintptr_t psp_mmio = get_psp_mmio_base();
+
+ if (!psp_mmio) {
+ printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n");
+ return CB_ERR;
+ }
+ *msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET);
return CB_SUCCESS;
}
\ No newline at end of file
--
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Gerrit-Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c
Gerrit-Change-Number: 83448
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
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Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83447?usp=email )
Change subject: soc/amd/common/psp_gen2: return status from soc_read_c2p38
......................................................................
soc/amd/common/psp_gen2: return status from soc_read_c2p38
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/
psp_gen2: simplify soc_read_c2p38") and is done as a preparation to
switch back to using the MMIO access to the PSP mailbox registers.
Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507
---
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
M src/soc/amd/common/block/psp/spl_fuse.c
4 files changed, 16 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83447/1
diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c
index be20fc8..a537bff 100644
--- a/src/soc/amd/common/block/psp/psb.c
+++ b/src/soc/amd/common/block/psp/psb.c
@@ -110,7 +110,11 @@
return CB_SUCCESS;
}
- status = soc_read_c2p38();
+ if (soc_read_c2p38(&status) != CB_SUCCESS) {
+ printk(BIOS_ERR, "PSP: Failed to get base address.\n");
+ return CB_ERR;
+ }
+
printk(BIOS_INFO, "PSB: HSTI = %x\n", status);
const u32 psb_test_status = status & PSB_TEST_STATUS_MASK;
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index f6efa21..104cabd 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -115,6 +115,6 @@
/* This command needs to be implemented by the generation specific code. */
int send_psp_command(u32 command, void *buffer);
-uint32_t soc_read_c2p38(void);
+enum cb_err soc_read_c2p38(uint32_t *msg_38_value);
#endif /* __AMD_PSP_DEF_H__ */
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 98baf86..98136d1 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -169,7 +169,8 @@
return 0;
}
-uint32_t soc_read_c2p38(void)
+enum cb_err soc_read_c2p38(uint32_t *msg_38_value)
{
- return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
-}
+ *msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
+ return CB_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/soc/amd/common/block/psp/spl_fuse.c b/src/soc/amd/common/block/psp/spl_fuse.c
index cb1fab0..b6e715a 100644
--- a/src/soc/amd/common/block/psp/spl_fuse.c
+++ b/src/soc/amd/common/block/psp/spl_fuse.c
@@ -8,12 +8,17 @@
static void psp_set_spl_fuse(void *unused)
{
int cmd_status = 0;
+ uint32_t c2p38 = 0;
struct mbox_cmd_late_spl_buffer buffer = {
.header = {
.size = sizeof(buffer)
}
};
- uint32_t c2p38 = soc_read_c2p38();
+
+ if (soc_read_c2p38(&c2p38) != CB_SUCCESS) {
+ printk(BIOS_ERR, "PSP: Failed to get base address.\n");
+ return;
+ }
if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) {
printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n");
--
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Gerrit-Change-Number: 83447
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
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Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83446?usp=email )
Change subject: soc/amd/common/block/psp_gen2: add get_psp_mmio_base
......................................................................
soc/amd/common/block/psp_gen2: add get_psp_mmio_base
Add get_psp_mmio_base which reads the PSP MMIO base address from the
hardware registers. Since this function will not only be called in
ramstage, but also in SMM, we can't just look for the specific domain
resource consumer like it is done for the IOAPICs in the northbridge,
but have to get this base address from the registers. In order to limit
the performance impact of this, the base address gets cached in a static
variable if the hardware lock bit of the corresponding base address
register is already set which means the base address can't change any
more before the next reset.
This is a preparation to move back to using MMIO access to the PSP
registers and will also enable cases that require the use of the MMIO
mapping of the PSP registers.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a
---
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
2 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83446/1
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 9def98b..f6efa21 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -108,6 +108,8 @@
#define PSP_INIT_TIMEOUT 10000 /* 10 seconds */
#define PSP_CMD_TIMEOUT 1000 /* 1 second */
+uintptr_t get_psp_mmio_base(void);
+
void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header);
/* This command needs to be implemented by the generation specific code. */
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index f647dcd..98baf86 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -3,6 +3,7 @@
#include <timer.h>
#include <types.h>
#include <amdblocks/psp.h>
+#include <amdblocks/root_complex.h>
#include <amdblocks/smn.h>
#include "psp_def.h"
@@ -10,6 +11,69 @@
#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */
#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */
+#define IOHC_MISC_PSP_MMIO_REG 0x2e0
+
+static uint64_t get_psp_mmio_mask(void)
+{
+ const struct non_pci_mmio_reg *mmio_regs;
+ size_t reg_count;
+ mmio_regs = get_iohc_non_pci_mmio_regs(®_count);
+
+ for (size_t i = 0; i < reg_count; i++) {
+ if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG)
+ return mmio_regs[i].mask;
+ }
+
+ printk(BIOS_ERR, "No PSP MMIO register description found.\n");
+ return 0;
+}
+
+/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM,
+ so we have to read this form the hardware registers */
+uintptr_t get_psp_mmio_base(void)
+{
+ static uintptr_t psp_mmio_base;
+ const struct domain_iohc_info *iohc;
+ size_t iohc_count;
+
+ if (psp_mmio_base)
+ return psp_mmio_base;
+
+ iohc = get_iohc_info(&iohc_count);
+ const uint64_t psp_mmio_mask = get_psp_mmio_mask();
+
+ if (!psp_mmio_mask)
+ return 0;
+
+ for (size_t i = 0; i < iohc_count; i++) {
+ const uint64_t reg64 =
+ smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG);
+
+ if (!(reg64 & IOHC_MMIO_EN))
+ continue;
+
+ const uint64_t base = reg64 & psp_mmio_mask;
+
+ if (ENV_X86_32 && base >= 4ull * GiB) {
+ printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n");
+ continue;
+ }
+
+ /* Don't cache the PSP MMIO base if the register isn't locked */
+ if (!(reg64 & BIT(8))) {
+ printk(BIOS_WARNING, "PSP MMIO in domain %ld isn't locked\n", i);
+ return base;
+ } else {
+ psp_mmio_base = base;
+ }
+ }
+
+ if (!psp_mmio_base)
+ printk(BIOS_ERR, "No usable PSP MMIO found.\n");
+
+ return psp_mmio_base;
+}
+
union pspv2_mbox_command {
u32 val;
struct pspv2_mbox_cmd_fields {
--
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