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Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Any idea where this is documented? I wonder why nobody else ran into this yet.
This is also the first time when the IOM was not ready before SiliconInit. All other TigerLake/AldeLake/RaptorLake platforms I dealt with did not have this issue.
In the ADL and RPL Core and Uncore BIOS Spec rev 0.9.2 (doc 627270) section 7.2.2.4.5 there is an information about disabling all TCSS IPs when IOM ready is not set. So, this is what FSP does here.
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Attention is currently required from: Eric Lai, Lawrence Chang, Paul Menzel, Tongtong Pan, Weimin Wu.
Weimin Wu has uploaded a new patch set (#14) to the change originally created by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/83376?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Weimin Wu, Code-Review+2 by Eric Lai
Change subject: mb/google/dedede: Create awasuki variant
......................................................................
mb/google/dedede: Create awasuki variant
Create the awasuki variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:351968527
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_AWASUKI
Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0
Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h
A src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h
A src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk
A src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt
A src/mainboard/google/dedede/variants/awasuki/overridetree.cb
8 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/83376/14
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Change subject: vc/google/chromeos: Add configurable compression for logo file in cbfs
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83420/comment/0aa16a0a_e29748a2?us… :
PS4, Line 12: Based on logo file content, enabling LZ4 compression could save upto
: ~2ms in boot time, with increase in file size ~2KB.
> What logo and what CPU, flash ROM chip was used for testing?
For brox
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Change subject: superio/ite: Enable common driver for GPIO and LED configuration
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83468/comment/ea5dfa14_71af049d?us… :
PS2, Line 11: withj
> typo
Done
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Hello Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: superio/ite: Enable common driver for GPIO and LED configuration
......................................................................
superio/ite: Enable common driver for GPIO and LED configuration
Enables the driver for ITE SIOs supporting the GPIO register layout
(confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs
with unavailable datasheets are unmodified).
Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM
and must then provide the number of GPIO sets specific to a chip
via SUPERIO_ITE_COMMON_NUM_GPIO_SETS.
Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/superio/ite/it8613e/Kconfig
M src/superio/ite/it8659e/Kconfig
M src/superio/ite/it8712f/Kconfig
M src/superio/ite/it8718f/Kconfig
M src/superio/ite/it8720f/Kconfig
M src/superio/ite/it8721f/Kconfig
M src/superio/ite/it8728f/Kconfig
M src/superio/ite/it8772f/Kconfig
M src/superio/ite/it8783ef/Kconfig
M src/superio/ite/it8784e/Kconfig
M src/superio/ite/it8786e/Kconfig
11 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/83468/3
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Change subject: security/vboot: Introduce vbnv_platform_init_cmos()
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83494/comment/613c7e33_0dc4dc80?us… :
PS2, Line 13: selection. Since VBNV is accessed via bank 0 (see the MC146818 driver),
Fixed.
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Hello Julius Werner, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: security/vboot: Introduce vbnv_platform_init_cmos()
......................................................................
security/vboot: Introduce vbnv_platform_init_cmos()
Most x86 platforms use CMOS as the vboot nvdata (VBNV) backend storage.
On some platforms such as AMD, certain CMOS registers must be configured
before accessing the CMOS RAM which contains VBNV. More precisely,
according to AMD's spec [1], the bit 4 of Register A of CMOS is bank
selection. Since VBNV is accessed via bank 0 (see the MC146818 driver),
the bit must be cleared before the VBNV can be successfully written to
CMOS. Saving VBNV to CMOS may fail in verstage, if CMOS has lost power.
In that case, all the CMOS registers would contain garbage data.
Therefore, for AMD platforms the bit must be cleared in verstage, prior
to the first save_vbnv_cmos() call.
Introduce vbnv_platform_init_cmos(), which is no-op by default, and can
be defined per platform. The function will be called from vbnv_init() if
VBOOT_VBNV_CMOS.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: Ic899a827bd6bb8ab1473f8c6c03b9fde96ea6823
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/security/vboot/vbnv.h
M src/security/vboot/vbnv_cmos.c
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/83494/3
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.
To fix the problem, define vbnv_platform_init_cmos() to configure the
Register A (RTC_FREQ_SELECT). Static assertions are also added to make
sure the whole VBNV is accessible via Bank 0 and that the written byte
doesn't contain RTC_AMD_BANK_SELECT (bit 4). Note that the kernel driver
also ensures RTC_AMD_BANK_SELECT isn't set for AMD [2].
[1] 48751_16h_bkdg.pdf
[2] lore.kernel.org/lkml/20220523165815.913462426@linuxfoundation.org
BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/include/pc80/mc146818rtc.h
M src/soc/amd/common/vboot/vbnv_cmos.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/3
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Select Bank 0 in vbnv_platform_init_cmos()
......................................................................
soc/amd: Select Bank 0 in vbnv_platform_init_cmos()
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.
To fix the problem, define vbnv_platform_init_cmos() to configure the
Register A (RTC_FREQ_SELECT). Static assertions are also added to make
sure the whole VBNV is accessible via Bank 0 and that the written byte
doesn't contain RTC_AMD_BANK_SELECT (bit 4). Note that the kernel driver
also ensures RTC_AMD_BANK_SELECT isn't set for AMD [2].
[1] 48751_16h_bkdg.pdf
[2] lore.kernel.org/lkml/20220523165815.913462426@linuxfoundation.org
BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/include/pc80/mc146818rtc.h
M src/soc/amd/common/vboot/vbnv_cmos.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/2
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