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Hello Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83573?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Code-Review+2 by Yidi Lin, Verified-1 by build bot (Jenkins)
Change subject: mb/google/rauru: Add MediaTek MT8196 reference board
......................................................................
mb/google/rauru: Add MediaTek MT8196 reference board
Add mainboard folder and drivers for new reference board 'Rauru'.
TEST=saw the coreboot uart log to bootblock
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e
---
A src/mainboard/google/rauru/Kconfig
A src/mainboard/google/rauru/Kconfig.name
A src/mainboard/google/rauru/Makefile.mk
A src/mainboard/google/rauru/board_info.txt
A src/mainboard/google/rauru/bootblock.c
A src/mainboard/google/rauru/chromeos.c
A src/mainboard/google/rauru/chromeos.fmd
A src/mainboard/google/rauru/devicetree.cb
A src/mainboard/google/rauru/mainboard.c
A src/mainboard/google/rauru/memlayout.ld
A src/mainboard/google/rauru/reset.c
A src/mainboard/google/rauru/romstage.c
12 files changed, 157 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83573/7
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Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83572/comment/2fd6f09d_1abe7796?us… :
PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'.
> Due to different SoCs architectures, register addresses, and driver parameters, if there are common […]
Is it really that different? Please mention it in the commit message, and also reference the datasheet name and revision.
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Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements
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Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83540/comment/43f0fcf4_fbbb8307?us… :
PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements
> Commit message is a bit wordy. Can you make it shorter? […]
Do you mean the summary/title?
I think your proposal is too general.
meteorlake to mtl is a good way to make it a little shorter though.
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Change subject: tree: Use boolean for "eist_enable"
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I would like to get in CB:77374 and others in first. Once that is done we can use a reproducible way for moving over the boolean options to true/false keywords.
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/83346/comment/ed7d3c37_7529ac5b?us… :
PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG),
> Acknowledged
I'm not sure where that clip came from, but the GPP_F14 gpio is not locked in mainboard/google/brya/variants/baseboard/brya/gpio.c
File src/mainboard/google/brya/variants/xol/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83346/comment/a0f56820_1ddcdefc?us… :
PS1, Line 347: register "generic.detect" = "1"
> Acknowledged
Won't this enable the interrupt? (IIRC, the touchpad is powered directly off of a power rail, so no independent way to disable interrupt for it.
If it enables the interrupt but there's no handler in coreboot for it / interrupt handler is in the kernel, couldn't that cause a problem if the touchpad interrupts before kernel is loaded?
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/83346/comment/52f01646_e940ec29?us… :
PS5, Line 128: LEVEL
Isn't this signal active-low?
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Change subject: xcompile: Drop CC_RT_EXTRA_GCC for PPC64
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Patch Set 1: Code-Review+2
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Change subject: bootsplash: Increase heap from 1 MB to 4 MB when bootsplash is enabled
......................................................................
Patch Set 2:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/83476/comment/21a302f4_8b0c4513?us… :
PS2, Line 507: default 0x400000 if BOOTSPLASH
Why not adding this as another default to src/Kconfig?
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83496/comment/65e4fc2b_d45ec0b0?us… :
PS6, Line 21: #| I2C1 | Disable |
: #| I2C2 | Touchscreen |
: #| I2C3 | Disable
Also you need to do disable I2C in FSP config like below:
```
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
```
https://review.coreboot.org/c/coreboot/+/83496/comment/08e25591_3278a218?us… :
PS6, Line 204: device pci 1c.7 on
: chip drivers/wifi/generic
: register "wake" = "GPE0_DW2_03"
: device pci 00.0 on end
: end
Does this board also support external/discrete Wifi? You need this only when discrete Wifi is used.
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