coreboot-gerrit July 2024

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[M] Change in coreboot[main]: mb/google/dedede/var/awasuki: Add initial GPIOs config
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83449?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/awasuki: Add initial GPIOs config ...................................................................... mb/google/dedede/var/awasuki: Add initial GPIOs config Configure GPIOs according to schematics revision 20240712. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/awasuki/Makefile.mk A src/mainboard/google/dedede/variants/awasuki/gpio.c 2 files changed, 66 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/awasuki/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/Makefile.mk new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/awasuki/gpio.c b/src/mainboard/google/dedede/variants/awasuki/gpio.c new file mode 100644 index 0000000..dfe14cd --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/gpio.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H1 : EN_PP3300_SD_U */ + PAD_NC(GPP_H1, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72 Gerrit-Change-Number: 83449 Gerrit-PatchSet: 8 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/dedede/var/awasuki: Generate 3 RAM IDs
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83427?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/awasuki: Generate 3 RAM IDs ...................................................................... mb/google/dedede/var/awasuki: Generate 3 RAM IDs Vendor DRAM Part Name Type SAMSUNG K4U6E3S4AB-MGCL LP4X SAMSUNG K4UBE3D4AB-MGCL LP4X MICRON MT53E1G32D2NP-046 WT:B LP4X BUG=b:351968527 TEST=Run part_id_gen tool without any errors Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427 Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk M src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt 3 files changed, 17 insertions(+), 2 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk index eace2e4..5348e2f 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/awasuki/memory src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt index fa24790..495df98 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/awasuki/memory src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt index 2499005..ca9e5c1 100644 --- a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name + +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/83427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Gerrit-Change-Number: 83427 Gerrit-PatchSet: 10 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/dedede: Create awasuki variant
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83376?usp=email ) Change subject: mb/google/dedede: Create awasuki variant ...................................................................... mb/google/dedede: Create awasuki variant Create the awasuki variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:351968527 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_AWASUKI Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/awasuki/data.vbt A src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h A src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h A src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk A src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/awasuki/overridetree.cb 9 files changed, 86 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Dolan Liu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 7c42120..f0ab1f5 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -34,6 +34,12 @@ select SOC_INTEL_JASPERLAKE select SPI_FLASH_SMM +config BOARD_GOOGLE_AWASUKI + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP + select SOC_INTEL_COMMON_BLOCK_IPU + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 def_bool n select BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -336,6 +342,7 @@ default "Taranza" if BOARD_GOOGLE_TARANZA default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "Awasuki" if BOARD_GOOGLE_AWASUKI config MAX_CPUS int @@ -380,6 +387,7 @@ default "taranza" if BOARD_GOOGLE_TARANZA default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "awasuki" if BOARD_GOOGLE_AWASUKI endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 6c1bf76..b470824 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -99,3 +99,6 @@ config BOARD_GOOGLE_WADDLEDOO bool "-> Waddledoo" + +config BOARD_GOOGLE_AWASUKI + bool "-> Awasuki" diff --git a/src/mainboard/google/dedede/variants/awasuki/data.vbt b/src/mainboard/google/dedede/variants/awasuki/data.vbt new file mode 100644 index 0000000..d082b19 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/data.vbt Binary files differ diff --git a/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h b/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h b/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/83376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Gerrit-Change-Number: 83376 Gerrit-PatchSet: 16 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Paul Menzel, Rishika Raj, Subrata Banik, Tarun. Nico Huber has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/c4ed6f96_5d0ef547?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > > Why the 32KiB? this makes it sound like coreboot would need that much. > > Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB > > would provide enough margin (unless something is wrong with the 512). > > The CAR stack defined in coreboot is also used by coreboot to fill up the FSP-M UPDs. It is evident that the existing romstage stack size (1KB) is too small to fulfill its intended purpose, as the 1KB reserved for coreboot's portion of the stack cannot even accommodate the stack-allocated FSPM_UPD structure itself. I see. Didn't expect this on the stack. Is that reasonable? Shouldn't that be linked into .bss or something? It's about 4KiB AFAICS, is that correct? > > Based on our debugging, we have observed instances where the vboot structure is also linked into CAR. As a result, we believe that 32KB is a reasonable size for us, given all of the factors involved. I don't understand this, how would a vboot structure linked into CAR affect the stack? What structure are you referring to specifically? -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Give PSP verstage 4K more space
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83564?usp=email ) Change subject: soc/amd/cezanne: Give PSP verstage 4K more space ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/psp_verstage_addr.h: https://review.coreboot.org/c/coreboot/+/83564/comment/9ced0144_cdf2b00b?us… : PS2, Line 20: #define PSP_VERSTAGE_STACK_START 0x42000 : #define PSP_VERSTAGE_STACK_SIZE (36K) The stack size and start address is a contract between PSP Bootloader and Verstage. So changing it here alone will break that contract. I am wondering if there are any clang compiler settings that can satisfy the memory layout requirements. Since we need to fix the original issue, let us just do ` cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);` in vbnv_platform_init_cmos for now and revisit switching to cmos_init(0) later. -- To view, visit https://review.coreboot.org/c/coreboot/+/83564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f53a45d67782d3e425f423d0715a45482b2edea Gerrit-Change-Number: 83564 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:38:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Limit power limits for low/no battery case
by YH Lin (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar, YH Lin. YH Lin has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83479?usp=email ) Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83479/comment/ec0ad43e_8e52815f?us… : PS7, Line 17: BUG=b:353395811 > Add me in bug to understand the background of this change. Thanks. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/83479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Gerrit-Change-Number: 83479 Gerrit-PatchSet: 7 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:35:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[XS] Change in coreboot[main]: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
by Karthik Ramasubramanian (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Jérémy Compostella, Paul Menzel, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83537?usp=email ) Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6122201914c40604f86dcca6025b55c595ef609e Gerrit-Change-Number: 83537 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:29:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboo...
by Subrata Banik (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Nico Huber, Paul Menzel, Rishika Raj, Tarun. Subrata Banik has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email ) Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83540/comment/d38adda1_1ee6782d?us… : PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements > Why the 32KiB? this makes it sound like coreboot would need that much. > Do we ever expect it to be more than 2KiB? If not, I'd guess that 4KiB > would provide enough margin (unless something is wrong with the 512). The CAR stack defined in coreboot is also used by coreboot to fill up the FSP-M UPDs. It is evident that the existing romstage stack size (1KB) is too small to fulfill its intended purpose, as the 1KB reserved for coreboot's portion of the stack cannot even accommodate the stack-allocated FSPM_UPD structure itself. Based on our debugging, we have observed instances where the vboot structure is also linked into CAR. As a result, we believe that 32KB is a reasonable size for us, given all of the factors involved. -- To view, visit https://review.coreboot.org/c/coreboot/+/83540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Gerrit-Change-Number: 83540 Gerrit-PatchSet: 5 Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 16:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: xcompile: Drop CC_RT_EXTRA_GCC for PPC64
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Michał Żygowski. Hello Michał Żygowski, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83577?usp=email to review the following change. Change subject: xcompile: Drop CC_RT_EXTRA_GCC for PPC64 ...................................................................... xcompile: Drop CC_RT_EXTRA_GCC for PPC64 It looks like some unused artifact: The PPC64 Makefile.mk doesn't pick it up. Also, the only other architecture using this (x86) has linker flags there, not compiler flags. Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/xcompile/xcompile 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83577/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3948811..b3012b5 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -415,7 +415,6 @@ TWIDTH="64" TSUPP="ppc64" TABI="linux-gnu" # there is no generic ABI on ppc64 - CC_RT_EXTRA_GCC="-mcpu=power8 -mbig-endian" } # Right now, the clang reference toolchain is not building compiler-rt builtins -- To view, visit https://review.coreboot.org/c/coreboot/+/83577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I734542db9ee5b62d9a39d303d4092cd83dfef54b Gerrit-Change-Number: 83577 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: Makefile.mk: Add a common link_stage function and use it
by Nico Huber (Code Review) 19 Jul '24

19 Jul '24

Attention is currently required from: Arthur Heymans, Julius Werner, Jérémy Compostella, Philipp Hug, Ron Minnich. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83574?usp=email ) Change subject: Makefile.mk: Add a common link_stage function and use it ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83574/comment/41d450b8_ccd35649?us… : PS2, Line 16: - the x86 --oformat is dropped as it is not needed. > > How would that look like? it's not just one linker script, right? […] So we'd have to duplicate that file for x86? Hmmm, looking through Makefiles, couldn't we just do something like ``` LDFLAGS_x86_32 += --oformat elf-i386 LDFLAGS_x86_64 += --oformat elf-x86-64 ``` ? `toolchain.mk` should add that to the respective stages (all on x86, I guess). -- To view, visit https://review.coreboot.org/c/coreboot/+/83574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Gerrit-Change-Number: 83574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Jul 2024 15:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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