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Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83563/comment/4eb877d2_28bb5f2c?us… :
PS2, Line 9: No assembly.inc file is being generated by romcc anymore.
> Please also mention "The `-I.` was only used in a single place that […]
Done. thx
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Hello Angel Pons, Jérémy Compostella, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83563?usp=email
to look at the new patch set (#3).
Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference
......................................................................
arch/x86/Makefile.mk: Remove obsolete romcc reference
No assembly.inc file is being generated by romcc anymore.
The -I. was only used in a single place that can use the common -Isrc
instead.
Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.mk
M src/northbridge/intel/sandybridge/mrc_wrapper.S
2 files changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/83563/3
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Hung-Te Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83572?usp=email )
Change subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83572/comment/16f23587_4cc0a255?us… :
PS4, Line 9: Add new folder and basic drivers for Mediatek SoC 'MT8196'.
> Approaches should be evaluated and changed. […]
Previous discussed in https://review.coreboot.org/c/coreboot/+/58640 ?
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83592?usp=email )
Change subject: device/azalia: Clear busy bit after failed verb command
......................................................................
device/azalia: Clear busy bit after failed verb command
The spec tells us to clear the busy bit manually after a timeout. Do
that and wait immediately, to detect further issues early. Also fix
some related comments and prints: Failures shouldn't be debug messa-
ges. And we are talking to the PIO interface of the controller, not
the codec. So this was never about the codec being ready.
Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/azalia_device.c
1 file changed, 13 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83592/1
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 4eed489..d39ef51 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -155,10 +155,8 @@
}
/*
- * Wait 50usec for the codec to indicate it is ready.
- * No response would imply that the codec is non-operative.
+ * Wait 50usec for the controller to indicate it is ready.
*/
-
static int wait_for_ready(u8 *base)
{
struct stopwatch sw;
@@ -179,7 +177,6 @@
* Wait for the codec to indicate that it accepted the previous command.
* No response would imply that the codec is non-operative.
*/
-
static int wait_for_valid(u8 *base)
{
struct stopwatch sw;
@@ -206,6 +203,16 @@
udelay(1);
}
+ /*
+ * HDA spec 1.0a "3.4.3 Offset 68h: Immediate Command Status"
+ * tells us to clear the busy bit explicitly, then poll until
+ * the controller is ready.
+ */
+ write32(base + HDA_ICII_REG, 0);
+ if (wait_for_ready(base) < 0) {
+ printk(BIOS_WARNING, "azalia_audio: controller is unresponsive.\n");
+ return -2;
+ }
return -1;
}
@@ -238,7 +245,7 @@
static bool codec_is_operative(u8 *base, const int addr)
{
if (wait_for_ready(base) < 0) {
- printk(BIOS_DEBUG, "azalia_audio: codec #%d not ready\n", addr);
+ printk(BIOS_WARNING, "azalia_audio: controller not ready\n");
return false;
}
@@ -246,7 +253,7 @@
write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) < 0) {
- printk(BIOS_DEBUG, "azalia_audio: codec #%d not valid\n", addr);
+ printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr);
return false;
}
return true;
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
Patch Set 7:
(2 comments)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83496/comment/168420b1_d2040751?us… :
PS6, Line 21: #| I2C1 | Disable |
: #| I2C2 | Touchscreen |
: #| I2C3 | Disable
> Also you need to do disable I2C in FSP config like below: […]
Done
https://review.coreboot.org/c/coreboot/+/83496/comment/656a34d2_a6154df7?us… :
PS6, Line 204: device pci 1c.7 on
: chip drivers/wifi/generic
: register "wake" = "GPE0_DW2_03"
: device pci 00.0 on end
: end
> Does this board also support external/discrete Wifi? You need this only when discrete Wifi is used.
Yes, need to support RTL8852BE PCIe Wifi module.
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Code-Review+1 by Dolan Liu, Verified+1 by build bot (Jenkins)
Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
mb/google/dedede/var/awasuki: Initialise overridetree
Initialise overridetree based on the schematics revision 20240715.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/variants/awasuki/Makefile.mk
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
A src/mainboard/google/dedede/variants/awasuki/ramstage.c
4 files changed, 212 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83496/7
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Change subject: mb/lenovo/t420: Use vendor default power limits
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83280/comment/c87e6759_1dca8886?us… :
PS6, Line 10:
How can users test the effects?
File src/mainboard/lenovo/t420/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83280/comment/91015e9d_8b7e7e69?us… :
PS6, Line 25: register "pp1_current_limit" = "32"
Where did you get the values from?
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Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83271/comment/898e5769_b7324b75?us… :
PS8, Line 8:
Can you elaborate?
https://review.coreboot.org/c/coreboot/+/83271/comment/174fd651_1ab16dc5?us… :
PS8, Line 10:
New message might be logged:
printk(BIOS_INFO, "%s: Programmable ratio limit for turbo mode is disabled\n",
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Change subject: cpu/intel/model_206ax: Allow package power limit clamping
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83270/comment/2f333cac_ecf52c82?us… :
PS8, Line 12: Tested on ThinkPad T420 with the i7-3940XM.
How can this be tested?
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