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Change subject: skl mainboards/dt: Move genx_dec settings into LPC device scope
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Patch Set 2: Code-Review+1
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Change subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
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Patch Set 3: Code-Review+1
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Change subject: soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500ms
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Patch Set 3: Code-Review+2
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Change subject: device/azalia: Rework the verb table
......................................................................
Patch Set 7:
(1 comment)
This change is ready for review.
Patchset:
PS7:
> @devel+coreboot@nsudsgaard.com I like the new design you are introducing. […]
Yes, I'm still interested.
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Change subject: device/azalia: Separate codec checking and initialization
......................................................................
Patch Set 12:
(2 comments)
File src/device/azalia_device.c:
https://review.coreboot.org/c/coreboot/+/80332/comment/19dae712_f5617d28?us… :
PS10, Line 274: >= 0
> i'd either use '== CB_SUCCESS' here or make codec_is_operative return a bool. […]
I agree, my original intent was to use booleans. Reverted.
https://review.coreboot.org/c/coreboot/+/80332/comment/cab35949_cd166f22?us… :
PS10, Line 280: if (!codec_can_init(codec_mask, base, i))
: continue;
: azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
> i'd keep the logic as it was before and not do the inverse logic and a continue like it's done now. […]
Done
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Hello Felix Held, Felix Singer, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80332?usp=email
to look at the new patch set (#12).
Change subject: device/azalia: Separate codec checking and initialization
......................................................................
device/azalia: Separate codec checking and initialization
This also changes how debug messages will be printed. I focused on
reducing clutter on the screen and made the style of the messages
consistent.
Before:
azalia_audio: Initializing codec #5
codec not ready.
azalia_audio: Initializing codec #4
codec not valid.
azalia_audio: Initializing codec #3
azalia_audio: viddid: ffffffff
azalia_audio: verb_size: 4
azalia_audio: verb loaded.
After:
azalia_audio: codec #5 not ready
azalia_audio: codec #4 not valid
azalia_audio: initializing codec #3...
azalia_audio: - vendor/device id: 0xffffffff
azalia_audio: - verb size: 4
azalia_audio: - verb loaded
Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
2 files changed, 40 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/80332/12
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Hello Felix Held, Felix Singer, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80332?usp=email
to look at the new patch set (#11).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: device/azalia: Separate codec checking and initialization
......................................................................
device/azalia: Separate codec checking and initialization
This also changes how debug messages will be printed. I focused on
reducing clutter on the screen and made the style of the messages
consistent.
Before:
azalia_audio: Initializing codec #5
codec not ready.
azalia_audio: Initializing codec #4
codec not valid.
azalia_audio: Initializing codec #3
azalia_audio: viddid: ffffffff
azalia_audio: verb_size: 4
azalia_audio: verb loaded.
After:
azalia_audio: codec #5 not ready
azalia_audio: codec #4 not valid
azalia_audio: initializing codec #3...
azalia_audio: - vendor/device id: 0xffffffff
azalia_audio: - verb size: 4
azalia_audio: - verb loaded
Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
2 files changed, 40 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/80332/11
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Change subject: acpi: Add support for DRHD size reporting
......................................................................
Patch Set 16:
(3 comments)
File src/acpi/acpi_dmar.c:
https://review.coreboot.org/c/coreboot/+/82429/comment/1ac3cd90_6228fa45?us… :
PS16, Line 68: (1 << (drhd->size + 12)
> That's just `size`, assuming it is a power of 2, if not we already have […]
If `size` is less than 4 KiB and `drhd->size` ends up being 0, it is treated as if it were 1 (4 KiB). But I agree with the suggested refactoring.
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/82429/comment/7a7ad5a1_c61dde80?us… :
PS16, Line 1855: u32
> Please use `size_t` for byte sizes.
(`size` can't be greater than 128 MiB anyway, but yes. One would need to use the 64-bit version of `log2` in the function definition).
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/82429/comment/8981df42_2d5d7971?us… :
PS15, Line 1852: unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,
: u16 segment, u64 bar, u32 size);
> > To avoid having to touch all platforms, would it make sense to have a specialised acpi_create_dmar […]
I considered that (even using the same function name), but I eventually decided that being explicit about the size (`_4k` suffix) was worth it.
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Change subject: soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically
......................................................................
Patch Set 19:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82431/comment/160a7dcd_fa92f3f9?us… :
PS12, Line 9: vtd_probe_bar_size is used to decide the BAR size.
> Thanks for suggestions. Updated in https://review.coreboot.org/c/coreboot/+/82429.
Done
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Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email )
Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
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Patch Set 8: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/83136/comment/0110bacc_ee6d7905?us… :
PS8, Line 141: pcidev_on_root(0, 0)
Is this always true? e.g. no IOAT on other sockets?
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