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Change subject: mb/google/fatcat: Add minimal code support for fatcat
......................................................................
Patch Set 4:
(11 comments)
File src/mainboard/google/fatcat/Kconfig:
https://review.coreboot.org/c/coreboot/+/83197/comment/af306157_8cc8b698?us… :
PS3, Line 52: select GBB_FLAG_FORCE_DEV_BOOT_USB
> NIT - Given these are alphabetical, this should be moved up 1 line
Acknowledged
https://review.coreboot.org/c/coreboot/+/83197/comment/e3ad6113_32b2838a?us… :
PS3, Line 94: DRIVER_TPM_I2C_ADDR
> NIT - should this be above DRIVER_TPM_I2C_BUS to be in alphabetical order, or should it stay here gi […]
Acknowledged
File src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/83197/comment/e580d7c9_22397060?us… :
PS3, Line 8: #include <baseboard/gpio.h>
> NIT - alphabetically, this should be first
Done
https://review.coreboot.org/c/coreboot/+/83197/comment/d7b7f1d6_f88a4e2a?us… :
PS3, Line 11: (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
> NIT - should these be alphabetized?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83197/comment/a627ff36_f08a5f09?us… :
PS3, Line 47: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
:
> NIT - alphabetize?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83197/comment/29fc8c77_3eec7528?us… :
PS3, Line 51: EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
> NIT - alphabetize?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83197/comment/d40e0dab_1a2206f1?us… :
PS3, Line 55: (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
: EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
> NIT - alphabetize?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83197/comment/163693a0_29fd6ee3?us… :
PS3, Line 68: #define EC_ENABLE_LID_SWITCH
: #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
: /* Enable EC backed PD MCU device in ACPI */
: #define EC_ENABLE_PD_MCU_DEVICE
: #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
: #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
: #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
:
: #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
: #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
> NIT - alphabetize?
Acknowledged
File src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/83197/comment/8f9e5612_1c18d2f7?us… :
PS3, Line 11: #define GPIO_PCH_WP 0
: /* GPIO IRQ for tight timestamps / wake support */
: #define EC_SYNC_IRQ 0
: /* eSPI virtual wire reporting */
: #define EC_SCI_GPI 0
:
> NIT - alphabetize?
Acknowledged
File src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c:
https://review.coreboot.org/c/coreboot/+/83197/comment/0efdeb69_fbf0839b?us… :
PS3, Line 22: variant_is_half_populated(void)
: {
> Does PTL have two channels? My understanding is that WCL will only have 1, in which case I wouldn't think this would be needed, but not sure about PTL.
PTL has two channel same as MTL
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/83197/comment/8cea4440_62bdcf2a?us… :
PS3, Line 12: #include <soc/gpio.h>
> NIT - alphabetize
Acknowledged
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Hello Nick Vaccaro, YH Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by YH Lin, Verified+1 by build bot (Jenkins)
Change subject: mb/google/fatcat: Add minimal code support for fatcat
......................................................................
mb/google/fatcat: Add minimal code support for fatcat
This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
A src/mainboard/google/fatcat/Kconfig
A src/mainboard/google/fatcat/Kconfig.name
A src/mainboard/google/fatcat/Makefile.mk
A src/mainboard/google/fatcat/board_info.txt
A src/mainboard/google/fatcat/bootblock.c
A src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
A src/mainboard/google/fatcat/chromeos.c
A src/mainboard/google/fatcat/chromeos.fmd
A src/mainboard/google/fatcat/dsdt.asl
A src/mainboard/google/fatcat/ec.c
A src/mainboard/google/fatcat/mainboard.c
A src/mainboard/google/fatcat/romstage.c
A src/mainboard/google/fatcat/smihandler.c
A src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
A src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
A src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h
A src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
A src/mainboard/google/fatcat/variants/baseboard/fatcat/memory.c
A src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
A src/mainboard/google/fatcat/variants/fatcat/gpio.c
A src/mainboard/google/fatcat/variants/fatcat/include/variant/ec.h
A src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h
23 files changed, 713 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/83197/4
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Change subject: mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)
......................................................................
Patch Set 13:
(1 comment)
This change is ready for review.
File src/mainboard/dell/xps_8300/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83104/comment/c41fe9a4_9544d9e0?us… :
PS12, Line 5: device domain 0x0 on
> All of the devices use the same subsystem ID. […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83104?usp=email
to look at the new patch set (#13).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)
......................................................................
mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)
Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).
The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.
Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environnement control
- GPIOs
- S3 Sleep mode
Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta(a)aliel.fr>
---
A src/mainboard/dell/xps_8300/Kconfig
A src/mainboard/dell/xps_8300/Kconfig.name
A src/mainboard/dell/xps_8300/Makefile.mk
A src/mainboard/dell/xps_8300/acpi/ec.asl
A src/mainboard/dell/xps_8300/acpi/platform.asl
A src/mainboard/dell/xps_8300/acpi/superio.asl
A src/mainboard/dell/xps_8300/board.fmd
A src/mainboard/dell/xps_8300/board_info.txt
A src/mainboard/dell/xps_8300/devicetree.cb
A src/mainboard/dell/xps_8300/dsdt.asl
A src/mainboard/dell/xps_8300/early_init.c
A src/mainboard/dell/xps_8300/gpio.c
A src/mainboard/dell/xps_8300/hda_verb.c
A src/mainboard/dell/xps_8300/mainboard.c
A src/mainboard/dell/xps_8300/smihandler.c
15 files changed, 480 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83104/13
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Change subject: mb: source site-local mainboard Kconfig.name and Kconfig files
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Not sure if I really like having a such include/source just
PS2:
> I like this idea, but does it need to be applied broadly? Maybe it's best to keep the added `source` […]
Not sure if I really like having a such include/source for every board while maybe just a few really use it
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Change subject: drivers/wifi: Support Wi-Fi 7 11be Enablement
......................................................................
Patch Set 9:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82207/comment/06425a37_be45aff2?us… :
PS9, Line 12: Wi-Fi 7 320 MHz is disabled default in some countries like Japan.
802.11be ?
https://review.coreboot.org/c/coreboot/+/82207/comment/f0fb8608_e3b3480f?us… :
PS9, Line 13: enable
enable/disable?
https://review.coreboot.org/c/coreboot/+/82207/comment/9fac7336_d79b65ea?us… :
PS9, Line 17: None
shouldn't this point to the rex fw branch ?
https://review.coreboot.org/c/coreboot/+/82207/comment/ca31714d_b0c1717e?us… :
PS9, Line 18: To test on Rex/Screebo
can you please add a meaningful TEST statement ? like how about DSD/DSM dump w/w.o this CL?
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Change subject: skl mainboards/dt: Move serirq setting into LPC device scope
......................................................................
Patch Set 3: Code-Review+1
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Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope
......................................................................
Patch Set 3: Code-Review+1
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