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Change subject: mb/google/nissa/var/pujjoga: Add wifi sar table
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
We need to rebase this first
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Change subject: mb/google/brox/var/brox: update thermal settings to start fan early
......................................................................
Patch Set 1: Code-Review+1
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Change subject: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/brox/var/lotso: Update dq map setting
......................................................................
Set Ready For Review
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Change subject: mb/google/brox/var/lotso: Update gpio setting
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/google/brox/variants/lotso/gpio.c:
https://review.coreboot.org/c/coreboot/+/82573/comment/c231c61a_974cef34?us… :
PS16, Line 5: include <soc/gpio.h>
> why not just <gpio. […]
<soc/gpio.h> would make it more intuitive where it comes from.
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Change subject: mb/google/brox/var/lotso: Update gpio setting
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/google/brox/variants/lotso/gpio.c:
https://review.coreboot.org/c/coreboot/+/82573/comment/cd001e02_e2fe99d2?us… :
PS16, Line 37: LOCK_CONFIG
> Should we use the LOCK variant only from RO such that RW cannot overwrite the pad config? If so then […]
Here we are using it from RW. Yes, lock the config such that OS cannot overwrite it.
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Attention is currently required from: Jérémy Compostella.
Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82793?usp=email )
Change subject: cpu/x86: Flip order for 1GB page tables to save a bit of space
......................................................................
cpu/x86: Flip order for 1GB page tables to save a bit of space
Linkers are very stupid when it comes to section alignments,
unfortunately. You'd think that when given a wildcard match like
*(.rodata.*) that contains a few small sections with 4K alignment and
many more sections with smaller alignments, they'd be clever enough to
place the 4K sections first and then fill in the gaps between them with
the less restricted sections. Alas, they don't... they'll just generate
a 3.9K NOP sled in front of each section. :( I guess the problem doesn't
come up often enough to be worth optimizing.
Thankfully, they're blindly placing the sections in input order but
they're still able to add in smaller data items after the last
4K-aligned section. For our 1GB page tables that's almost enough,
because we only really have one small 4K-aligned object (PM4LE). So by
reordering things such that that table comes last, we can help the
linker waste a little less space. (There is still some wastage between
the start of .rodata and the first 4K-aligned object which I don't think
we can do anything about. Even if we put them all in separate sections,
they might not be placed at the start of .rodata but they still get
placed randomly in input order without any consideration about how much
alignment adjustment that would require.)
Change-Id: I1c97f504e17d99c77a18c795b4f2b3e59849b5e4
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/cpu/x86/64bit/pt1G.S
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/82793/1
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3ddb620..0fc6cfd 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -17,13 +17,13 @@
#define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
-.global PM4LE
-.align 4096
-PM4LE:
-.quad _GEN_DIR(PDE_table)
-
.align 4096
PDE_table: /* identity map 1GiB pages * 512 */
.rept 512
.quad _GEN_PAGE(0x40000000 * ((. - PDE_table) >> 3))
.endr
+
+.global PM4LE
+.align 4096
+PM4LE:
+.quad _GEN_DIR(PDE_table)
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Change subject: cpu/x86: Make 1GB paging the default
......................................................................
cpu/x86: Make 1GB paging the default
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaining
most boards will build the smaller 1GB pages. Only CPUs that actually
don't support that feature should manually select the option to build
2MB pages, which to my knowledge(?) is only QEMU.
Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/cpu/qemu-x86/Kconfig
M src/cpu/x86/64bit/Makefile.mk
M src/cpu/x86/Kconfig
3 files changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82792/1
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index b5ff6f0..221a7ba 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -7,6 +7,7 @@
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
+ select NEED_SMALL_2MB_PAGE_TABLES # QEMU doesn't support 1GB pages
if CPU_QEMU_X86
diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk
index b24e4d7..1fda087 100644
--- a/src/cpu/x86/64bit/Makefile.mk
+++ b/src/cpu/x86/64bit/Makefile.mk
@@ -3,10 +3,10 @@
all_x86-y += mode_switch.S
all_x86-y += mode_switch2.S
-ifeq ($(CONFIG_USE_1G_PAGES_TLB),y)
-PAGETABLE_SRC := pt1G.S
-else
+ifeq ($(CONFIG_NEED_SMALL_2MB_PAGE_TABLES),y)
PAGETABLE_SRC := pt.S
+else
+PAGETABLE_SRC := pt1G.S
endif
all_x86-y += $(PAGETABLE_SRC)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index ec1fa13..83a5e16 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -152,12 +152,14 @@
bool
default n
-config USE_1G_PAGES_TLB
+config NEED_SMALL_2MB_PAGE_TABLES
bool
default n
help
- Select this option to enable access to up to 512 GiB of memory
- by using 1 GiB large pages.
+ Select this option from boards/SoCs that do not support the Page1GB
+ CPUID feature (CPUID.80000001H:EDX.bit26). This started being
+ available in all CPUs around 2010ish, so nowadays this option is
+ mostly just needed for emulation targets.
config SMM_ASEG
bool
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