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Change subject: cpu/x86: Flip order for 1GB page tables to save a bit of space
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Patch Set 1: Code-Review+2
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Change subject: cpu/x86: Make 1GB paging the default
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Hello Vamshi Krishna Gopal, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brox: Update verb table to refine speaker amp DC offset
......................................................................
mb/google/brox: Update verb table to refine speaker amp DC offset
DC offset of class-D amplifier is larger than expectation in Brox.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek.
BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier is less than 3mV
Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
Signed-off-by: Terry Cheong <htcheong(a)chromium.org>
---
M src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82794/2
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Change subject: mb/google/brox: Update verb table to refine speaker amp DC offset
......................................................................
mb/google/brox: Update verb table to refine speaker amp DC offset
DC offset of class-D amplifier is larger than expectation in Brox.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek.
BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier is less than 3mV
Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
---
M src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82794/1
diff --git a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h
index c0b0eb0..f47bdfe 100644
--- a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h
+++ b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h
@@ -113,6 +113,11 @@
0x02046A0C,
0x02050008,
0x02046A0C,
+ /* Class D calibration */
+ 0x05850000,
+ 0x0584F880,
+ 0x05850000,
+ 0x0584F880,
};
const u32 pc_beep_verbs[] = {
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Change subject: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/82781/comment/71c4da29_67b79410?us… :
PS4, Line 119: select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT
> Currently none of the ADL-N boards select FSP_TYPE_IOT. Do we know if this is
> correct or rather an oversight because it wasn't necessary before?
You are correct, because all ADL-N boards are coming from the Google ChromeOS project, where we use the client FSP. It is possible that IOT uses of coreboot are not upstreaming their code.
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Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper
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Patch Set 6:
(1 comment)
File src/superio/nuvoton/common/common.c:
https://review.coreboot.org/c/coreboot/+/82632/comment/5297675d_2561705a?us… :
PS6, Line 79: * Clear case open pin 0 status.
> But how if we clear it on boot? Assuming somebody opened the case, tampered, closed […]
If you refer to the datasheet, that bit is a write-clear - I write a 1 there to clear the status. If the switch trips again, status will be set again, and userspace will know. Handling then will be up to the OS.
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