June 2024 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier, Paul Menzel, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83265?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... soc/intel/common: Add fpt_support to override CSME and HECI disables Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI Shell and various Operating Systems. However, FPT requires the Intel ME to be enabled, and for the HECI interface to be visible. Add a runtime option `fpt_support`, which users can use to stop HECI and the Intel ME from being disabled so this tool will work. TEST=Boot starbook_rpl with edk2 payload, and flash BIOS region with FPT.efi. Change-Id: I695fa96c5057303730492139904dfcc1d989880b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83265/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/80705?usp=email ) Change subject: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II ...................................................................... Patch Set 7: (3 comments) File src/mainboard/starlabs/byte_adl/cmos.default: https://review.coreboot.org/c/coreboot/+/80705/comment/39eb4399_d21a99be?us… : PS7, Line 9: Balanced > for a device which is always connected to external power, any reason to not use performance here? For most no, but some people care about power consumption and heat on these (they're fanless) File src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80705/comment/b6fac31f_84068d73?us… : PS7, Line 4: SaGv_Enabled > necessary/desired for a desktop device? setting to highest freq only should save some RAM training t […] You mean remove it? I thought it didn't limit performance https://review.coreboot.org/c/coreboot/+/80705/comment/127bc728_b24fb5b4?us… : PS7, Line 143: end > EC interface isn't used for fan control etc? There's no fan, EC controls the power button and power sequence, nothing else -- To view, visit https://review.coreboot.org/c/coreboot/+/80705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Gerrit-Change-Number: 80705 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 21:08:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: i2c/drivers/generic: Add support for including a CDM
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81409?usp=email ) Change subject: i2c/drivers/generic: Add support for including a CDM ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/generic/chip.h: https://review.coreboot.org/c/coreboot/+/81409/comment/77e70e85_c5210dca?us… : PS2, Line 86: in > is? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81409?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b Gerrit-Change-Number: 81409 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 21:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XL] Change in coreboot[main]: mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/80706?usp=email ) Change subject: mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V ...................................................................... Patch Set 5: (3 comments) File Documentation/mainboard/starlabs/starlite_adl.md: https://review.coreboot.org/c/coreboot/+/80706/comment/cfeeff5b_b48942a0?us… : PS5, Line 19: - 9560 2230 WiFi / Bluetooth > I thought it used a soldered CNVi module? Done https://review.coreboot.org/c/coreboot/+/80706/comment/bf948765_046dd628?us… : PS5, Line 32: ype-A > 2x Type-C Done File src/mainboard/starlabs/starlite_adl/board_info.txt: https://review.coreboot.org/c/coreboot/+/80706/comment/810c3016_5cbb7897?us… : PS5, Line 3: laptop > convertible? I think laptop is the closest match out of: desktop|server|laptop|half|mini|settop|"eval"|sbc|emulation|misc) -- To view, visit https://review.coreboot.org/c/coreboot/+/80706?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8724e578c21353032b844b20b868348580ff561b Gerrit-Change-Number: 80706 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 21:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XL] Change in coreboot[main]: mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80706?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V ...................................................................... mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starlite-specification Change-Id: I8724e578c21353032b844b20b868348580ff561b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starlite_adl.md A src/mainboard/starlabs/starlite_adl/Kconfig A src/mainboard/starlabs/starlite_adl/Kconfig.name A src/mainboard/starlabs/starlite_adl/Makefile.mk A src/mainboard/starlabs/starlite_adl/acpi/ec.asl A src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl A src/mainboard/starlabs/starlite_adl/acpi/sleep.asl A src/mainboard/starlabs/starlite_adl/acpi/superio.asl A src/mainboard/starlabs/starlite_adl/board_info.txt A src/mainboard/starlabs/starlite_adl/bootblock.c A src/mainboard/starlabs/starlite_adl/cmos.default A src/mainboard/starlabs/starlite_adl/cmos.layout A src/mainboard/starlabs/starlite_adl/dsdt.asl A src/mainboard/starlabs/starlite_adl/hda_verb.c A src/mainboard/starlabs/starlite_adl/include/variants.h A src/mainboard/starlabs/starlite_adl/mainboard.c A src/mainboard/starlabs/starlite_adl/smbios.c A src/mainboard/starlabs/starlite_adl/spd/Makefile.mk A src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8.spd.hex A src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk A src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd A src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt A src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb A src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c A src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c A src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c A src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c A src/mainboard/starlabs/starlite_adl/variants/mk_v/vboot.fmd A src/mainboard/starlabs/starlite_adl/vboot.c 30 files changed, 1,502 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/80706/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80706?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8724e578c21353032b844b20b868348580ff561b Gerrit-Change-Number: 80706 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier, Paul Menzel. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83265?usp=email to look at the new patch set (#3). Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... soc/intel/common: Add fpt_support to override CSME and HECI disables Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI Shell and various Operating Systems. However, FPT requires the Intel ME to be enabled, and for the HECI interface to be visible. Add a runtime option `fpt_support`, which users can use to stop HECI and the Intel ME from being disabled so this tool will work. TEST=Boot starbook_rpl with edk2 payload, and flash BIOS region with FPT.efi. Change-Id: I695fa96c5057303730492139904dfcc1d989880b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83265/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Matt DeVillier, Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83265?usp=email ) Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83265/comment/2db48783_f48ef3af?us… : PS1, Line 9: Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI > > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […] Done https://review.coreboot.org/c/coreboot/+/83265/comment/596210d3_68c7d0c0?us… : PS1, Line 15: > Please add TEST=. Done File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/83265/comment/b32fadf9_10213dfe?us… : PS1, Line 1328: me_state > variable should be `cmos_me_state` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 30 Jun 2024 20:55:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83265?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... soc/intel/common: Add fpt_support to override CSME and HECI disables Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI Shell and various Operating Systems. However, FPT requires the Intel ME to be enabled, and for the HECI interface to be visible. Add a runtime option `fpt_support`, which users can use to stop HECI and the Intel ME from being disabled so this tool will work. TEST=Boot starbook_rpl with edk2 payload, and flash BIOS region with FPT.efi. Change-Id: I695fa96c5057303730492139904dfcc1d989880b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83265/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
by Anastasios Koutian (Code Review) June 30, 2024

June 30, 2024

Attention is currently required from: Angel Pons. Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email ) Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83271/comment/9688554d_52e3b895?us… : PS2, Line 9: Tested on ThinkPad T420 with the i7-3940XM. > Ack. A potential way to go about this: […] Added commit with vendor default values on top -- To view, visit https://review.coreboot.org/c/coreboot/+/83271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Gerrit-Change-Number: 83271 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 19:03:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasios Koutian <akoutian2(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/lenovo/t420: Use vendor default power limits
by Anastasios Koutian (Code Review) June 30, 2024

June 30, 2024

Anastasios Koutian has removed Alexander Couzens from this change. ( https://review.coreboot.org/c/coreboot/+/83280?usp=email ) Change subject: mb/lenovo/t420: Use vendor default power limits ...................................................................... Removed reviewer Alexander Couzens <lynxis(a)fe80.eu>. -- To view, visit https://review.coreboot.org/c/coreboot/+/83280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: deleteReviewer Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b Gerrit-Change-Number: 83280 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com>

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