coreboot-gerrit June 2024

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[M] Change in coreboot[main]: autoport: Factor out GPIO config generation
by Nicholas Chin (Code Review) 01 Jul '24

01 Jul '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83286?usp=email ) Change subject: autoport: Factor out GPIO config generation ...................................................................... autoport: Factor out GPIO config generation Intel chipsets from ICH7 through Lynxpoint use same GPIO register format and thus use similar code in gpio.c. Factor out the code to generate gpio.c from bd82x6x.go so that it other chipsets added to autoport can use it. This was originally written by Iru Cai in his Haswell autoport patch in CB:30890; I have simply split out the code to a separate commit as it is a separate logical change. TEST=Generated output is identical before and after this patch when run against logs from a Dell Latitude E6430 Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/autoport/bd82x6x.go A util/autoport/gpio_common.go 2 files changed, 115 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83286/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index d31cd6b..2dc4961 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -1,120 +1,12 @@ package main -import ( - "fmt" - "os" -) +import "fmt" type bd82x6x struct { variant string node *DevTreeNode } -func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, - val uint32, set uint, partno int, constraint uint32) { - - max := uint(32) - if set == 3 { - max = 12 - } - - bits := [6][2]string{ - {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, - {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, - {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, - {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, - {"GPIO_NO_INVERT", "GPIO_INVERT"}, - {"GPIO_NO_BLINK", "GPIO_BLINK"}, - } - - for i := uint(0); i < max; i++ { - if (constraint>>i)&1 == 1 { - fmt.Fprintf(sb, " .gpio%d = %s,\n", - (set-1)*32+i, - bits[partno][(val>>i)&1]) - } - } -} - -func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { - var constraint uint32 - gpio := Create(ctx, "gpio.c") - defer gpio.Close() - - AddBootBlockFile("gpio.c", "") - AddROMStageFile("gpio.c", "") - - Add_gpl(gpio) - gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") - - addresses := [3][6]int{ - {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, - {0x30, 0x34, 0x38, 0x64, -1, -1}, - {0x40, 0x44, 0x48, 0x68, -1, -1}, - } - - for set := 1; set <= 3; set++ { - for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { - addr := addresses[set-1][partno] - if addr < 0 { - continue - } - fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", - set, set, part) - - constraint = 0xffffffff - switch part { - case "direction": - /* Ignored on native mode */ - constraint = inteltool.GPIO[uint16(addresses[set-1][0])] - case "level": - /* Level doesn't matter for input */ - constraint = inteltool.GPIO[uint16(addresses[set-1][0])] - constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] - case "reset": - /* Only show reset */ - constraint = inteltool.GPIO[uint16(addresses[set-1][3])] - case "invert": - /* Only on input and only show inverted GPIO */ - constraint = inteltool.GPIO[uint16(addresses[set-1][0])] - constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] - constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] - case "blink": - /* Only on output and only show blinking GPIO */ - constraint = inteltool.GPIO[uint16(addresses[set-1][0])] - constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] - constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] - } - b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) - gpio.WriteString("};\n\n") - } - } - - gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; -`) -} - func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] if !ok { @@ -168,7 +60,7 @@ SouthBridge = &b inteltool := ctx.InfoSource.GetInteltool() - b.GPIO(ctx, inteltool) + GPIO(ctx, inteltool) KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true diff --git a/util/autoport/gpio_common.go b/util/autoport/gpio_common.go new file mode 100644 index 0000000..a869dce --- /dev/null +++ b/util/autoport/gpio_common.go @@ -0,0 +1,113 @@ +/* code to generate common GPIO code for Intel 6/7/8 Series Chipset */ + +package main + +import ( + "fmt" + "os" +) + +func writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if (constraint>>i)&1 == 1 { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddBootBlockFile("gpio.c", "") + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") + + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Gerrit-Change-Number: 83286 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Paul Menzel (Code Review) 01 Jul '24

01 Jul '24

Paul Menzel has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: > You both were right, disabling `CONFIG_CONSOLE_SERIAL` reduced the boot time to 1. […] Thank you again for the logs and responding. Memory training (without MRC cache or booting the first time with empty cache) takes the expected time (around 30 seconds): aoostar/wtr_r1/24.05-388-g1f5a221a51/2024-06-29T22_51_16Z/coreboot_timestamps.txt […] 950:calling FspMemoryInit 168,130 (108,717) 951:returning from FspMemoryInit 31,738,002 (31,569,872) […] 90:starting to load payload 32,460,379 (392) 15:starting LZMA decompress (ignore for x86) 32,460,440 (60) 16:finished LZMA decompress (ignore for x86) 33,443,057 (982,617) The long decompression time (above and below) is surprising to me though: aoostar/wtr_r1/24.05-173-gbf1166e8a6/2024-06-07T06_16_41Z/coreboot_timestamps.txt […] 962:calling FspMultiPhaseSiInit 634,246 (0) 963:returning from FspMultiPhaseSiInit 1,108,438 (474,192) […] 90:starting to load payload 1,127,814 (363) 15:starting LZMA decompress (ignore for x86) 1,127,875 (60) 16:finished LZMA decompress (ignore for x86) 2,099,501 (971,625) The payload is 1.3 MB in size and despite cbfstool claiming it’s not compressed, the config says it is (`CONFIG_COMPRESSED_PAYLOAD_LZMA=y`). fallback/payload 0x1647c0 simple elf 1288296 none -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 17 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 22:31:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Federico Amedeo Izzo <federico(a)izzo.pro> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: Add starfive visionfive2 mainboard
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83285?usp=email ) Change subject: Add starfive visionfive2 mainboard ...................................................................... Add starfive visionfive2 mainboard tested: not working: Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I212b7fad0c2dbbdd93a76b30409b0d6ca6066763 --- A src/mainboard/starfive/Kconfig A src/mainboard/starfive/Kconfig.name A src/mainboard/starfive/visionfive2/Kconfig A src/mainboard/starfive/visionfive2/Kconfig.name A src/mainboard/starfive/visionfive2/Makefile.inc A src/mainboard/starfive/visionfive2/board_info.txt A src/mainboard/starfive/visionfive2/bootblock.c A src/mainboard/starfive/visionfive2/cbfs_spi.c A src/mainboard/starfive/visionfive2/devicetree.cb A src/mainboard/starfive/visionfive2/dts-old/include/gpio.h A src/mainboard/starfive/visionfive2/dts-old/include/starfive,jh7110-clock.h A src/mainboard/starfive/visionfive2/dts-old/include/starfive,jh7110-crg.h A src/mainboard/starfive/visionfive2/dts-old/include/starfive,jh7110-pmu.h A src/mainboard/starfive/visionfive2/dts-old/include/starfive,jh7110-reset.h A src/mainboard/starfive/visionfive2/dts-old/include/thermal.h A src/mainboard/starfive/visionfive2/dts-old/jh7110-pinfunc.h A src/mainboard/starfive/visionfive2/dts-old/jh7110-starfive-visionfive-2-v1.2a.dts A src/mainboard/starfive/visionfive2/dts-old/jh7110-starfive-visionfive-2-v1.3b.dts A src/mainboard/starfive/visionfive2/dts-old/jh7110-starfive-visionfive-2.dtsi A src/mainboard/starfive/visionfive2/dts-old/jh7110.dtsi A src/mainboard/starfive/visionfive2/dts/dt-bindings/clock/starfive,jh7110-crg.h A src/mainboard/starfive/visionfive2/dts/dt-bindings/gpio/gpio.h A src/mainboard/starfive/visionfive2/dts/dt-bindings/power/starfive,jh7110-pmu.h A src/mainboard/starfive/visionfive2/dts/dt-bindings/reset/starfive,jh7110-crg.h A src/mainboard/starfive/visionfive2/dts/dt-bindings/thermal/thermal.h A src/mainboard/starfive/visionfive2/dts/jh7110-pinfunc.h A src/mainboard/starfive/visionfive2/dts/jh7110-starfive-visionfive-2-v1.3b.dts A src/mainboard/starfive/visionfive2/dts/jh7110-starfive-visionfive-2.dtsi A src/mainboard/starfive/visionfive2/dts/jh7110.dtsi A src/mainboard/starfive/visionfive2/dts/move-dts.sh A src/mainboard/starfive/visionfive2/fixup_fdt.c A src/mainboard/starfive/visionfive2/mainboard.c A src/mainboard/starfive/visionfive2/romstage.c A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-can-pdm-pwmdac.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-can-pdm-pwmdac.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-can-pdm-pwmdac.dtb.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-can-pdm-pwmdac.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-dvp-rgb2hdmi.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-dvp-rgb2hdmi.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-evb-dvp-rgb2hdmi.dtb.d.pre.tmp A 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src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-A11.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-ac108.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-ac108.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-ac108.dtb.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-ac108.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-sof-wm8960.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-sof-wm8960.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-sof-wm8960.dtb.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-sof-wm8960.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-v1.3b.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-v1.3b.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-v1.3b.dtb.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-v1.3b.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-wm8960.dtb.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-wm8960.dtb.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-wm8960.dtb.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/.jh7110-starfive-visionfive-2-wm8960.dtb.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/Makefile A src/mainboard/starfive/visionfive2/starfive-v6.6/dtbs-list A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-can.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-can.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-can.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-can.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-rgb2hdmi.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-rgb2hdmi.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-rgb2hdmi.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-rgb2hdmi.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-sdio.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-sdio.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-sdio.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-sdio.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-spi.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-spi.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-spi.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-spi.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart4-emmc.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart4-emmc.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart4-emmc.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart4-emmc.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart5-pwm.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart5-pwm.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart5-pwm.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/.jh7110-evb-overlay-uart5-pwm.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/Makefile A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-can.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-can.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-rgb2hdmi.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-rgb2hdmi.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-sdio.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-sdio.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-spi.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-spi.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-uart4-emmc.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-uart4-emmc.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-uart5-pwm.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/evb-overlay/jh7110-evb-overlay-uart5-pwm.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7100-beaglev-starlight.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7100-common.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7100-starfive-visionfive-v1.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7100.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-clk.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-can-pdm-pwmdac.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-can-pdm-pwmdac.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-dvp-rgb2hdmi.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-dvp-rgb2hdmi.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-i2s-ac108.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-i2s-ac108.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-pcie-i2s-sd.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-pcie-i2s-sd.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-pinctrl.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-spi-uart2.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-spi-uart2.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart1-rgb2hdmi.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart1-rgb2hdmi.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart4-emmc-spdif.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart4-emmc-spdif.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart5-pwm-i2c-tdm.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-uart5-pwm-i2c-tdm.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-usbdevice.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb-usbdevice.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-evb.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-fpga.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-pinfunc.h A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-A10.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-A11.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-ac108.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-ac108.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-sof-wm8960.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-tdm.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-v1.2a.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-v1.3b.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-v1.3b.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-wm8960.dtb A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2-wm8960.dts A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110-starfive-visionfive-2.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/jh7110.dtsi A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-can.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-can.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-can.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-can.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-uart3-i2c.dtbo.cmd A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-uart3-i2c.dtbo.d.dtc.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-uart3-i2c.dtbo.d.pre.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/.vf2-overlay-uart3-i2c.dtbo.dts.tmp A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/Makefile A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/vf2-overlay-can.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/vf2-overlay-can.dtso A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/vf2-overlay-uart3-i2c.dtbo A src/mainboard/starfive/visionfive2/starfive-v6.6/vf2-overlay/vf2-overlay-uart3-i2c.dtso A src/soc/starfive/jh7110/Kconfig A src/soc/starfive/jh7110/Makefile.inc A src/soc/starfive/jh7110/TRM_FAULTS.md A src/soc/starfive/jh7110/bootblock.c A src/soc/starfive/jh7110/cbmem.c A src/soc/starfive/jh7110/chip.c A src/soc/starfive/jh7110/clint.c A src/soc/starfive/jh7110/clock_reset.c A src/soc/starfive/jh7110/ddrregs.c A src/soc/starfive/jh7110/gpio.c A src/soc/starfive/jh7110/include/soc/addressmap.h A src/soc/starfive/jh7110/include/soc/clock.h A src/soc/starfive/jh7110/include/soc/gpio.h A src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h A src/soc/starfive/jh7110/include/soc/sdram.h A src/soc/starfive/jh7110/include/soc/spi.h A src/soc/starfive/jh7110/jh7110-pinfunc.h A src/soc/starfive/jh7110/memlayout.ld A src/soc/starfive/jh7110/otp.c A src/soc/starfive/jh7110/sdram.c A src/soc/starfive/jh7110/spi_internal.h A src/soc/starfive/jh7110/uart.c 217 files changed, 90,230 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/83285/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I212b7fad0c2dbbdd93a76b30409b0d6ca6066763 Gerrit-Change-Number: 83285 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: arch/riscv: Allow adding OpenSBI as external blob
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Philipp Hug, Ron Minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83284?usp=email ) Change subject: arch/riscv: Allow adding OpenSBI as external blob ...................................................................... arch/riscv: Allow adding OpenSBI as external blob The reasoning is that even though vendors currently tend to open source their OpenSBI implementation, they often do so in their own repository. So instead of adding all possible source repositories as submodules, we shall allow specifying a path to an already compiled OpenSBI ELF file. This is similar of what we currently do on ARM64 with the BL31 binary. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I6592ad90a254ca4ac9a6cee89404ad49274f0dea --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83284/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index b570b01..5d887ea 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -56,15 +56,29 @@ Load OpenSBI after payload has been loaded and use it to provide the SBI and to handover control to payload. +if RISCV_OPENSBI + +config OPENSBI_BLOB + string "Include OpenSBI ELF binary blob" + depends on RISCV_OPENSBI + help + If enabled it allows to specify a file path to an already compiled OpenSBI binary. + If disabled the OpenSBI binary will be compiled from upstream OpenSBI repository. + This option is discouraged as compatibility with out-of-tree blobs may break anytime. + +config OPENSBI_BLOB_PATH + string "Path to external opensbi.elf" + depends on OPENSBI_BLOB + help + Absolute (or relative to coreboot directory) path to the OpenSBI ELF file. + config OPENSBI_PLATFORM string - depends on RISCV_HAS_OPENSBI help The OpenSBI platform to build for. config OPENSBI_TEXT_START hex - depends on RISCV_HAS_OPENSBI help The linking address used to build opensbi. @@ -78,6 +92,8 @@ that is the mode usually used for the payload. If the hart does not support Supervisor mode OpenSBI will again look for a hart that does support it. +endif # RISCV_OPENSBI + config ARCH_RISCV_U # U (user) mode is for programs. bool diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index d5defea..be8962a 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -169,7 +169,12 @@ FW_PAYLOAD=n \ FW_TEXT_START=$(CONFIG_OPENSBI_TEXT_START) -$(OPENSBI): $(OPENSBI_TARGET) +# build upstream OpenSBI source tree +opensbi-source-y = $(OPENSBI_TARGET) +# get OpenSBI from specified binary +opensbi-source-$(OPENSBI_BLOB) = $(call strip_quotes,$(OPENSBI_BLOB_PATH)) + +$(OPENSBI): $(opensbi-source-y) cp $< $@ OPENSBI_CBFS := $(CONFIG_CBFS_PREFIX)/opensbi -- To view, visit https://review.coreboot.org/c/coreboot/+/83284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6592ad90a254ca4ac9a6cee89404ad49274f0dea Gerrit-Change-Number: 83284 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: arch/riscv: Add PMP print function
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83283?usp=email ) Change subject: arch/riscv: Add PMP print function ...................................................................... arch/riscv: Add PMP print function For easier debugging it is useful to have a function that prints the PMP regions. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I6ab1531c65b14690e37aecf57ff441bf22db1ce5 --- M src/arch/riscv/include/arch/pmp.h M src/arch/riscv/pmp.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/83283/1 diff --git a/src/arch/riscv/include/arch/pmp.h b/src/arch/riscv/include/arch/pmp.h index f98adf7..273ccfe 100644 --- a/src/arch/riscv/include/arch/pmp.h +++ b/src/arch/riscv/include/arch/pmp.h @@ -11,6 +11,8 @@ */ int pmp_entries_num(void); +void print_pmp_regions(void); + /* reset PMP setting */ void reset_pmp(void); diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index b643441..18bb704 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "commonlib/bsd/helpers.h" #include <arch/encoding.h> #include <stdint.h> #include <arch/pmp.h> @@ -314,6 +315,52 @@ pmp_entry_used_mask |= 1 << idx; } +/* prints the pmp regions by reading the PMP address and configuration registers */ +void print_pmp_regions(void) +{ + uintptr_t prev_pmpaddr = 0; + uintptr_t base = 0; + uintptr_t size = 0; + const char *mode; + for (int i = 0; i < pmp_entries_num(); i++) { + uintptr_t pmpcfg = read_pmpcfg(i); + uintptr_t pmpaddr = read_pmpaddr(i); + if ((pmpcfg & PMP_A) == 0) { + continue; // PMP entry is disabled + } else if (pmpcfg & PMP_NA4) { + base = pmpaddr << PMP_SHIFT; + size = 4; + mode = "NA4"; + } else if (pmpcfg & PMP_NAPOT) { + unsigned int count_trailing_ones = 0; + base = pmpaddr; + while (base) { + if ((base & 1) == 0) + break; // we got a zero + count_trailing_ones++; + base >>= 1; + } + size = 8 << count_trailing_ones; + base = (pmpaddr & ~((2 << count_trailing_ones) - 1)) >> PMP_SHIFT; + mode = "NAPOT"; + } else if (pmpcfg & PMP_TOR) { + base = pmpaddr; + size = pmpaddr - prev_pmpaddr; + mode = "TOR"; + } + + printk(BIOS_DEBUG, "base: 0x%lx, size: 0x%lx, perm: %c%c%c, mode: %s, locked: %d\n", + base, size, + (pmpcfg & PMP_R) ? 'r' : ' ', + (pmpcfg & PMP_W) ? 'w' : ' ', + (pmpcfg & PMP_X) ? 'x' : ' ', + mode, + (pmpcfg & PMP_L) ? 1 : 0); + + prev_pmpaddr = pmpaddr; + } +} + /* reset PMP setting */ void reset_pmp(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/83283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab1531c65b14690e37aecf57ff441bf22db1ce5 Gerrit-Change-Number: 83283 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: util/ifdtool: dump SPI modes from FLCOMP
by Alexander Goncharov (Code Review) 30 Jun '24

30 Jun '24

Alexander Goncharov has posted comments on this change by Alexander Goncharov. ( https://review.coreboot.org/c/coreboot/+/83282?usp=email ) Change subject: util/ifdtool: dump SPI modes from FLCOMP ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83282/comment/4ea7a318_65451ff9?us… : PS1, Line 9: These fields are documented in the Alder Lake-S Client Platform SPI : Programming Guide, but they are not presented in the Skylake-LP : Client Platform SPI Programming Guide It would be nice if someone who has access to Coffee Lake SPI guide could confirm that these fields are presented -- To view, visit https://review.coreboot.org/c/coreboot/+/83282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2 Gerrit-Change-Number: 83282 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Sun, 30 Jun 2024 21:34:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/ifdtool: dump SPI modes from FLCOMP
by Alexander Goncharov (Code Review) 30 Jun '24

30 Jun '24

Alexander Goncharov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83282?usp=email ) Change subject: util/ifdtool: dump SPI modes from FLCOMP ...................................................................... util/ifdtool: dump SPI modes from FLCOMP These fields are documented in the Alder Lake-S Client Platform SPI Programming Guide, but they are not presented in the Skylake-LP Client Platform SPI Programming Guide Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2 Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> --- M util/ifdtool/ifdtool.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/83282/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 033ccf4..32b2081 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -737,6 +737,15 @@ else freq = (fcba->flcomp >> 17) & 7; decode_espi_frequency(freq); + + printf("\n Quad I/O Read: %s", + (fcba->flcomp & (1 << 15)) ? "enabled" : "disabled"); + printf("\n Quad Output Read: %s", + (fcba->flcomp & (1 << 14)) ? "enabled" : "disabled"); + printf("\n Dual I/O Read: %s", + (fcba->flcomp & (1 << 13)) ? "enabled" : "disabled"); + printf("\n Dual Output Read: %s", + (fcba->flcomp & (1 << 12)) ? "enabled" : "disabled"); } else { printf("\n Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 17) & 7); -- To view, visit https://review.coreboot.org/c/coreboot/+/83282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2 Gerrit-Change-Number: 83282 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net>

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[M] Change in coreboot[main]: util/ifdtool: fix spacing issues
by Alexander Goncharov (Code Review) 30 Jun '24

30 Jun '24

Alexander Goncharov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83281?usp=email ) Change subject: util/ifdtool: fix spacing issues ...................................................................... util/ifdtool: fix spacing issues Ensure consistent spacing around colons in bit fields, operators, statements and function calls. Found by the linter (check-style). Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83281/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 1c3e810..033ccf4 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -51,20 +51,20 @@ * protected region start address, where bit 0-11 of * the start address are assumed to be zero. */ - uint32_t start:15; + uint32_t start : 15; /* Specifies read protection is enabled */ - uint32_t read_protect_en:1; + uint32_t read_protect_en : 1; /* * End Address: bit 16-30 of the GPRD represents the * protected region end address, where bit 0-11 of * the end address are assumed to be 0xfff. */ - uint32_t end:15; + uint32_t end : 15; /* Specifies write protection is enabled */ - uint32_t write_protect_en:1; + uint32_t write_protect_en : 1; } __packed data; uint32_t value; @@ -133,9 +133,9 @@ /* Scan for FD signature */ for (i = 0; i < (size - 4); i += 4) { - if (*(uint32_t *) (image + i) == 0x0FF0A55A) { + if (*(uint32_t *)(image + i) == 0x0FF0A55A) { found = 1; - break; // signature found. + break; // signature found. } } @@ -144,7 +144,7 @@ return NULL; } - struct fdbar *fdb = (struct fdbar *) (image + i); + struct fdbar *fdb = (struct fdbar *)(image + i); return PTR_IN_RANGE(fdb, image, size) ? fdb : NULL; } @@ -168,9 +168,8 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fcba *fcba = (struct fcba *) (image + ((fdb->flmap0 & 0xff) << 4)); + struct fcba *fcba = (struct fcba *)(image + ((fdb->flmap0 & 0xff) << 4)); return PTR_IN_RANGE(fcba, image, size) ? fcba : NULL; - } static struct fmba *find_fmba(char *image, int size) @@ -178,7 +177,7 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmba *fmba = (struct fmba *) (image + ((fdb->flmap1 & 0xff) << 4)); + struct fmba *fmba = (struct fmba *)(image + ((fdb->flmap1 & 0xff) << 4)); return PTR_IN_RANGE(fmba, image, size) ? fmba : NULL; } @@ -211,7 +210,7 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmsba *fmsba = (struct fmsba *) (image + ((fdb->flmap2 & 0xff) << 4)); + struct fmsba *fmsba = (struct fmsba *)(image + ((fdb->flmap2 & 0xff) << 4)); return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL; } @@ -355,7 +354,7 @@ if (region_type >= max_regions) { fprintf(stderr, "Invalid region type %d.\n", region_type); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } flreg = frba->flreg[region_type]; @@ -387,7 +386,7 @@ { if (region_type >= max_regions) { fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } return region_names[region_type].pretty; @@ -452,7 +451,7 @@ * 4 bytes of space. */ if (sorted[i] == frba) - return MIN((sorted[i+1] - sorted[i])/4, MAX_REGIONS); + return MIN((sorted[i + 1] - sorted[i]) / 4, MAX_REGIONS); } /* Never reaches this point */ return 0; @@ -717,7 +716,7 @@ printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", - (fcba->flcomp & (1 << 30))?"":"not "); + (fcba->flcomp & (1 << 30)) ? "" : "not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); @@ -725,7 +724,7 @@ printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); printf("\n Fast Read Support: %ssupported", - (fcba->flcomp & (1 << 20))?"":"not "); + (fcba->flcomp & (1 << 20)) ? "" : "not "); if (is_platform_with_100x_series_pch() && chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { printf("\n Read eSPI/EC Bus Frequency: "); @@ -977,7 +976,7 @@ static void dump_vtba(const struct vtba *vtba, int vtl) { int i; - int max_len = sizeof(struct vtba)/sizeof(struct vscc); + int max_len = sizeof(struct vtba) / sizeof(struct vscc); int num = (vtl >> 1) < max_len ? (vtl >> 1) : max_len; printf("ME VSCC table:\n"); @@ -997,10 +996,10 @@ for (i = 0; i < 4; i++) { printf("%02x:", i << 4); for (j = 0; j < 16; j++) - printf(" %02x", oem[(i<<4)+j]); - printf ("\n"); + printf(" %02x", oem[(i << 4) + j]); + printf("\n"); } - printf ("\n"); + printf("\n"); } static void dump_fd(char *image, int size) @@ -1124,11 +1123,11 @@ sorted_regions[count_regions] = region; // basically insertion sort - for (int i = count_regions-1; i >= 0 ; i--) { - if (sorted_regions[i].base > sorted_regions[i+1].base) { + for (int i = count_regions - 1; i >= 0; i--) { + if (sorted_regions[i].base > sorted_regions[i + 1].base) { struct region tmp = sorted_regions[i]; - sorted_regions[i] = sorted_regions[i+1]; - sorted_regions[i+1] = tmp; + sorted_regions[i] = sorted_regions[i + 1]; + sorted_regions[i + 1] = tmp; } } count_regions++; @@ -1858,8 +1857,8 @@ { if (ifd_version >= IFD_VERSION_2) { printf("%sting the HAP bit to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[0] |= (1 << 16); else @@ -1868,8 +1867,8 @@ if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("%sting the ICH_MeDisable, MCH_MeDisable, " "and MCH_AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) { /* MCH_MeDisable */ fmsba->data[0] |= 1; @@ -1884,8 +1883,8 @@ } } else { printf("%sting the AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[10] |= (1 << 7); else @@ -2570,7 +2569,7 @@ // generate new filename if (new_filename == NULL) { - new_filename = (char *) malloc((strlen(filename) + 5) * sizeof(char)); + new_filename = (char *)malloc((strlen(filename) + 5) * sizeof(char)); if (!new_filename) { printf("Out of memory.\n"); exit(EXIT_FAILURE); -- To view, visit https://review.coreboot.org/c/coreboot/+/83281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd Gerrit-Change-Number: 83281 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net>

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[S] Change in coreboot[main]: soc/intel/common: Add fpt_support to override CSME and HECI disables
by Sean Rhodes (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Matt DeVillier, Paul Menzel, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83265?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/common: Add fpt_support to override CSME and HECI disables ...................................................................... soc/intel/common: Add fpt_support to override CSME and HECI disables Intels FPT (Flash Programming Tool) can be used to flash coreboot via the EFI Shell and various Operating Systems. However, FPT requires the Intel ME to be enabled, and for the HECI interface to be visible. Add a runtime option `fpt_support`, which users can use to stop HECI and the Intel ME from being disabled so this tool will work. TEST=Boot starbook_rpl with edk2 payload, and flash BIOS region with FPT.efi. Change-Id: I695fa96c5057303730492139904dfcc1d989880b Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83265/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I695fa96c5057303730492139904dfcc1d989880b Gerrit-Change-Number: 83265 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II
by Sean Rhodes (Code Review) 30 Jun '24

30 Jun '24

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/80705?usp=email ) Change subject: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II ...................................................................... Patch Set 7: (3 comments) File src/mainboard/starlabs/byte_adl/cmos.default: https://review.coreboot.org/c/coreboot/+/80705/comment/39eb4399_d21a99be?us… : PS7, Line 9: Balanced > for a device which is always connected to external power, any reason to not use performance here? For most no, but some people care about power consumption and heat on these (they're fanless) File src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80705/comment/b6fac31f_84068d73?us… : PS7, Line 4: SaGv_Enabled > necessary/desired for a desktop device? setting to highest freq only should save some RAM training t […] You mean remove it? I thought it didn't limit performance https://review.coreboot.org/c/coreboot/+/80705/comment/127bc728_b24fb5b4?us… : PS7, Line 143: end > EC interface isn't used for fan control etc? There's no fan, EC controls the power button and power sequence, nothing else -- To view, visit https://review.coreboot.org/c/coreboot/+/80705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132 Gerrit-Change-Number: 80705 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Jun 2024 21:08:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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