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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82049?usp=email )
Change subject: soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pin
......................................................................
soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pin
Explicitly assign a value of 0 to the first value of the
pcie_swizzle_pin enum. This won't change the behavior, but clarifies
that the actual values of the enum elements matter.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90
---
M src/soc/amd/common/block/pci/pci_routing_info.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/82049/1
diff --git a/src/soc/amd/common/block/pci/pci_routing_info.c b/src/soc/amd/common/block/pci/pci_routing_info.c
index ac72553..5d5f355 100644
--- a/src/soc/amd/common/block/pci/pci_routing_info.c
+++ b/src/soc/amd/common/block/pci/pci_routing_info.c
@@ -7,7 +7,7 @@
#include <types.h>
enum pcie_swizzle_pin {
- PIN_A,
+ PIN_A = 0,
PIN_B,
PIN_C,
PIN_D,
--
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Change subject: soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
......................................................................
soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq'
to better describe what it's doing. This struct element contains the
number of the northbridge IOAPIC IRQ input the bridge IRQ is connected
to signal power management or error reporting IRQs. Right now, coreboot
doesn't put this information into the ACPI bytecode.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155
---
M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
M src/soc/amd/common/fsp/pci/pci_routing_info.c
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/82048/1
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
index f862bf9..db8b704 100644
--- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
@@ -57,7 +57,7 @@
uint8_t devfn;
uint8_t group;
uint8_t swizzle;
- uint8_t irq;
+ uint8_t bridge_irq; /* also called 'map' */
} __packed;
void populate_pirq_data(void);
diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c
index 5e3c368..96ea1ff 100644
--- a/src/soc/amd/common/fsp/pci/pci_routing_info.c
+++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c
@@ -34,9 +34,9 @@
routing_table_entries = routing_hob->num_of_entries;
for (size_t i = 0; i < routing_table_entries; ++i) {
- printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n",
+ printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, bridge irq: %u\n",
PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn),
- routing_table[i].group, routing_table[i].swizzle, routing_table[i].irq);
+ routing_table[i].group, routing_table[i].swizzle, routing_table[i].bridge_irq);
}
*entries = routing_table_entries;
--
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Change subject: Makefile: Always disable warnings for out-of-order record fields
......................................................................
Makefile: Always disable warnings for out-of-order record fields
We added this as a GCC 10 quirk, but of course by now there are many
more versions with this flag. Stable GCC 10.1 was released almost 4
years ago and libhwbase is mostly used with coreboot's toolchain and
newer ones. So we don't have to keep compatibility with older GCC
releases.
Change-Id: I1131ebbdde71cd6223a9ea650512eec601401cc3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/libhwbase/+/82052
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Makefile
1 file changed, 1 insertion(+), 4 deletions(-)
Approvals:
Nico Huber: Verified
Angel Pons: Looks good to me, approved
diff --git a/Makefile b/Makefile
index fb4c43c..e8d864e 100644
--- a/Makefile
+++ b/Makefile
@@ -43,8 +43,6 @@
CC = $(CROSS_COMPILE)gcc
GNATBIND = $(CROSS_COMPILE)gnatbind
-GCC_MAJOR = $(shell echo __GNUC__ | $(CC) -E - 2>/dev/null | tail -1)
-
CFLAGS += -Wuninitialized -Wall -Werror
CFLAGS += -pipe -g
CFLAGS += -Wstrict-aliasing -Wshadow
@@ -89,8 +87,7 @@
# .Y Disable information messages for why package spec needs body:
# Those messages are annoying. But don't forget to enable those,
# if you need the information.
-ADAFLAGS += -gnatwa.eeD.HHTU.U.W.Y
-ADAFLAGS += $(if $(filter 10,$(GCC_MAJOR)),-gnatw_R)
+ADAFLAGS += -gnatwa.eeD.HHTU.U.W.Y_R
# Disable style checks for now
ADAFLAGS += -gnatyN
--
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Change subject: Makefile: Always disable warnings for out-of-order record fields
......................................................................
Patch Set 1: Verified+1
(1 comment)
Patchset:
PS1:
Confirmed that I can compile `gfx_test` with GCC 13.
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Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/622e87fb_1eae7435 :
PS7, Line 125: device ref pch_espi on
> I wasn't sure how to configure it to be perfectly honest. […]
In Intel PCH, the I/O Range is configured using registers in the LPC/eSPI controller:
```
eSPI Generic I/O Range 1 (ESPI_LGIR1)
eSPI Generic I/O Range 2 (ESPI_LGIR2)
eSPI Generic I/O Range 3 (ESPI_LGIR3)
eSPI Generic I/O Range 4 (ESPI_LGIR4)
```
You can make a dump and check their values with the vendor's firmware to set the corresponding `genX_dec` values in the devicetree.
My point is, its probable that some of the EC/HWM registers are unavailable because of the incorrect IO range. But this is just a guess.
There was a similar problem on the asrock board (an example for nuvoton HWM - https://github.com/coreboot/coreboot/blob/main/src/mainboard/asrock/h110m/d…), which was resolved by this way. However, in your case, ITE makes the issue more difficult.
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Change subject: mb/google/rex/var/deku: Configure GPIO
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82035/comment/43e2705e_984c6c42 :
PS2, Line 7: Configure GPIO
The text below would have been the better, as more specific, summary.
https://review.coreboot.org/c/coreboot/+/82035/comment/45bd8f4e_7308f568 :
PS2, Line 9: Set unused pin to NC internal PU 20K
Would be nice, if you elaborated next time. Was the board design updated?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67499?usp=email )
Change subject: gma tgl: Add connector programming
......................................................................
Patch Set 38:
(1 comment)
File common/tigerlake/hw-gfx-gma-connectors.adb:
https://review.coreboot.org/c/libgfxinit/+/67499/comment/14dfc645_580d0631 :
PS37, Line 393: --if Port_Cfg.Display = HDMI then
: -- if Port_Cfg.Port in Combo_Port then
: -- Combo_Phy.Enable_HDMI (Port_Cfg.Port);
: -- else
: -- TC.Enable_HDMI (Port_Cfg.Port);
: -- end if;
: --end if;
> Acknowledged
The PRM clearly states this should happen after the pipe setup and Linux seems
to follow. Needs further investigation.
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Change subject: tgl plls: Disable warnings about unused variable
......................................................................
tgl plls: Disable warnings about unused variable
Looks like this is yet-to-be-implemented code. To be able to build-test
other changes, turn off some warnings about the `PLLs` variable.
TEST=Run this and make sure all builds pass:
for f in configs/*
do
make distclean
make DEBUG=1 cnf=$f -j$(nproc)
done
Change-Id: I51a14f7a9d6d6d930b9239ed5d0f61c45f2f123b
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/81852
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: Nico Huber <nico.h(a)gmx.de>
---
M common/tigerlake/hw-gfx-gma-plls.adb
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Nico Huber: Verified; Looks good to me, approved
diff --git a/common/tigerlake/hw-gfx-gma-plls.adb b/common/tigerlake/hw-gfx-gma-plls.adb
index bf58f57..2823870 100644
--- a/common/tigerlake/hw-gfx-gma-plls.adb
+++ b/common/tigerlake/hw-gfx-gma-plls.adb
@@ -27,7 +27,14 @@
end record;
type PLL_State_Array is array (Configurable_DPLLs) of PLL_State;
+
+ pragma Warnings (Off, "unused variable ""PLLs""",
+ Reason => "Not yet implemented.");
+ pragma Warnings (Off, "variable ""PLLs"" is assigned but never read",
+ Reason => "Not yet implemented.");
PLLs : PLL_State_Array;
+ pragma Warnings (On, "variable ""PLLs"" is assigned but never read");
+ pragma Warnings (On, "unused variable ""PLLs""");
procedure Initialize is
begin
--
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82010?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
......................................................................
mb/aoostar: Add AOOSTAR R1 (WTR_R1)
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM
slot. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT
and USB-C Alt-DP Power Delivery.
Working:
- Automatic FAN control (IT8613E SuperIO)
- M.2 NVME slot
- 2x SATA ports (Issue on 3.5" HDD, see below)
- USB 2.0 ports
- USB 3.0 ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- MicroSD card reader
- ASPM (Unavailable on stock)
- Linux/Windows UEFI booting with EDK2
Broken:
- Power button (OFF->ON broken, ON->OFF works)
- 3.5" SATA HDDs (Detected only after reboot)
Untested:
- Internal audio
- S3
My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).
The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the SuperIO registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
Any hint on the power button or 3.5" HDD issue is welcome.
VDT extracted from vendor BIOS.
Compiled with FSP GOP video initialization, using IFD descriptor,
ME blob and vgabios blob (ID 8086,0406) extracted from vendor BIOS.
The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O.
Internal flashing works, as flash is not read/write protected.
Patchset 5: Re-enabled dptf, added default options to Kconfig.
Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works
Patchset 8: Fixed microSD card reader
Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro>
---
A src/mainboard/aoostar/Kconfig
A src/mainboard/aoostar/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Kconfig
A src/mainboard/aoostar/wtr_r1/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Makefile.mk
A src/mainboard/aoostar/wtr_r1/board_info.txt
A src/mainboard/aoostar/wtr_r1/bootblock.c
A src/mainboard/aoostar/wtr_r1/data.vbt
A src/mainboard/aoostar/wtr_r1/devicetree.cb
A src/mainboard/aoostar/wtr_r1/dsdt.asl
A src/mainboard/aoostar/wtr_r1/gpio.h
A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
12 files changed, 744 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/8
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Change subject: bsd/cbfs_serialized: Check the cbfs_file size also when using clang
......................................................................
Patch Set 3: -Code-Review
(1 comment)
Patchset:
PS3:
Actually, we probably shouldn't do this either, same reason as the other patch.
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Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>
Gerrit-Comment-Date: Tue, 23 Apr 2024 18:44:53 +0000
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