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Change subject: drivers/intel/touch: Add driver for Intel Touch Controller and Devices
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Separate the ELAN and WACOM support to another patch?
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Change subject: mb/google/nissa/var/craaskov: Disable external fivr
......................................................................
mb/google/nissa/var/craaskov: Disable external fivr
In next phase, craaskov will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message
BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/craaskov/overridetree.cb
M src/mainboard/google/brya/variants/craaskov/variant.c
2 files changed, 27 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/81607/2
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(
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)Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller
......................................................................
include/device/pci_ids.h: Add DIDs for MTL Touch controller
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for
THC0, and 0x7e4b for THC1.
0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0
and THC1 respectively.
Refer MTL EDS vol 1: 640228.
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim(a)intel.com>
---
M src/include/device/pci_ids.h
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Kyoung Il Kim: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 1ae09f0..7831d5b 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4721,6 +4721,12 @@
#define PCI_DID_INTEL_EHL_GBE_PSE_0 0x4BA0
#define PCI_DID_INTEL_EHL_GBE_PSE_1 0x4BB0
+/* Intel Touch Controller */
+#define PCI_DID_INTEL_MTL_THC0_1 0x7e48
+#define PCI_DID_INTEL_MTL_THC0_2 0x7e49
+#define PCI_DID_INTEL_MTL_THC1_1 0x7e4a
+#define PCI_DID_INTEL_MTL_THC1_2 0x7e4b
+
#define PCI_VID_COMPUTONE 0x8e0e
#define PCI_DID_COMPUTONE_IP2EX 0x0291
#define PCI_DID_COMPUTONE_PG 0x0302
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Change subject: soc/intel/xeon_sp: Share unlock_pam_regions()
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/81619/comment/04f5111a_d1e398e0 :
PS2, Line 27: unlock_pam_regions();
> Oh sorry for my suggestion to move it back to romstage. I see that it happens after FSP-M. […]
Sure, no problem. I restored the previous version.
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Change subject: soc/intel/xeon_sp: Share unlock_pam_regions()
......................................................................
soc/intel/xeon_sp: Share unlock_pam_regions()
unlock_pam_regions() is needed for SKX and CPX. Put the codes into
chip_gen1.c so that it could be shared among SoC generations.
After shared, unlock_pam_regions() is still called from SKX and
CPX SoC specific codes. SPR will also use chip_gen1.c, but it will
not call unlock_pam_regions().
TEST=intel/archercity CRB
Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/chip.c
4 files changed, 30 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81619/3
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Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> maybe you can mention in commet.
added info to the commit messages.
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Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller
......................................................................
include/device/pci_ids.h: Add DIDs for MTL Touch controller
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for
THC0, and 0x7e4b for THC1.
0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0
and THC1 respectively.
Refer MTL EDS vol 1: 640228.
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9
---
M src/include/device/pci_ids.h
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/81330/3
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 33:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81316/comment/014ba0be_5d25a8ce :
PS32, Line 20:
> Sorry, last thing. Please also add the datasheet names and revisions.
Sorry, the SoC is not launched yet and hence the datasheet is not made public. We could add some README later after the product launch.
Patchset:
PS32:
> Sure, for the parts to split from this one, any suggestions?
I tentatively split this one into 2. Could you please have a look?
https://review.coreboot.org/c/coreboot/+/81316https://review.coreboot.org/c/coreboot/+/81628
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This patch is split from https://review.coreboot.org/c/coreboot/+/81316
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
soc/intel/xeon_sp: Use default soc_get_ioapic_info
intel/common/block/acpi provides default soc_get_ioapic_info for
single IOAPIC model. Use the default soc_get_ioapic_info when
XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and
later.
TEST=intel/archercity CRB
Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/81628/1
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index de63ced..9ee8d6a 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -90,6 +90,7 @@
return map;
}
+#if CONFIG(XEON_SP_HAVE_IIO_IOAPIC)
static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1];
size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
@@ -126,6 +127,7 @@
return index;
}
+#endif
void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
{
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Gerrit-Change-Number: 81628
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