coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: tree: Drop unused <post.h>
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81815?usp=email ) Change subject: tree: Drop unused <post.h> ...................................................................... tree: Drop unused <post.h> Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81815 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/common/psp_verstage/post.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: Angel Pons: Looks good to me, approved Varshit Pandya: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/common/psp_verstage/post.c b/src/soc/amd/common/psp_verstage/post.c index 5b429c9..04c03d2 100644 --- a/src/soc/amd/common/psp_verstage/post.c +++ b/src/soc/amd/common/psp_verstage/post.c @@ -2,7 +2,6 @@ #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> -#include <post.h> void arch_post_code(u8 value) { diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 1ddfe8b..aabc54d 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/pci.h> #include <intelblocks/acpi.h> -#include <post.h> #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/soc_util.h> diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 99f5bd9..7e831ab 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -8,7 +8,6 @@ #include <device/pci_def.h> #include <soc/pci_devs.h> #include <intelblocks/acpi.h> -#include <post.h> #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/soc_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593 Gerrit-Change-Number: 81815 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix non-local header treated as local
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81813?usp=email ) Change subject: soc/intel/alderlake: Fix non-local header treated as local ...................................................................... soc/intel/alderlake: Fix non-local header treated as local Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/systemagent.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index a9c00a9..b08e3a3 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -19,7 +19,7 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <spi_flash.h> -#include "stddef.h" +#include <stddef.h> /* * SoC implementation -- To view, visit https://review.coreboot.org/c/coreboot/+/81813?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0 Gerrit-Change-Number: 81813 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
by Shelley Chen (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81789?usp=email to look at the new patch set (#2). Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO ...................................................................... mb/google/brox: Initialize NOTE_BOOK_MODE GPIO The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also initializing NOTE_BOOT_MODE to and output GPIO. BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change. Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81789/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Gerrit-Change-Number: 81789 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: tree: Drop unused <delay.h>
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81812?usp=email ) Change subject: tree: Drop unused <delay.h> ...................................................................... tree: Drop unused <delay.h> Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/drivers/spi/issi.c M src/ec/clevo/it5570e/commands.c M src/mainboard/google/cherry/mainboard.c M src/mainboard/purism/librem_jsl/bootblock.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/meteorlake/finalize.c M src/soc/intel/meteorlake/systemagent.c M src/soc/mediatek/mt8195/pcie.c M src/soc/qualcomm/common/display/mdss.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c M src/soc/sifive/fu740/gpio.c M src/soc/sifive/fu740/spi.c 16 files changed, 0 insertions(+), 16 deletions(-) Approvals: Varshit Pandya: Looks good to me, but someone else must approve Jonathon Hall: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c index 884fcdb..f6ccc5e 100644 --- a/src/drivers/spi/issi.c +++ b/src/drivers/spi/issi.c @@ -3,7 +3,6 @@ #include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> -#include <delay.h> #include "spi_flash_internal.h" diff --git a/src/ec/clevo/it5570e/commands.c b/src/ec/clevo/it5570e/commands.c index 7a85b8f..8f53bb1 100644 --- a/src/ec/clevo/it5570e/commands.c +++ b/src/ec/clevo/it5570e/commands.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <ec/acpi/ec.h> #include <swab.h> diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 0e78f62..19638c9 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -3,7 +3,6 @@ #include <boardid.h> #include <bootmode.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/mmio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/purism/librem_jsl/bootblock.c b/src/mainboard/purism/librem_jsl/bootblock.c index e97fc4d..e0f480e 100644 --- a/src/mainboard/purism/librem_jsl/bootblock.c +++ b/src/mainboard/purism/librem_jsl/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <delay.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> #include <gpio.h> diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 5264d48..2e3a97b 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -4,7 +4,6 @@ #include <device/pci_def.h> #include <spd.h> -#include "delay.h" #include "gm45.h" void raminit_thermal(const sysinfo_t *sysinfo) diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index b06330c..19ec585 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -3,7 +3,6 @@ #include <assert.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> -#include <delay.h> #include <device/pci_ops.h> #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index ffb5e82..2fed93d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -6,7 +6,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <delay.h> #include <device/pci_ops.h> #include <mrc_cache.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 3df23f2..a9c00a9 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -11,7 +11,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/power_limit.h> diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 06ea13cc..64beb85 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -4,7 +4,6 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <device/pci.h> #include <gpio.h> #include <intelblocks/cse.h> diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 6b445af..774a99f 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -5,7 +5,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/power_limit.h> diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index fa5bbd7..7f60d68 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <device/resource.h> -#include <delay.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/early_init.h> diff --git a/src/soc/qualcomm/common/display/mdss.c b/src/soc/qualcomm/common/display/mdss.c index 1ff923d..a1c13ee 100644 --- a/src/soc/qualcomm/common/display/mdss.c +++ b/src/soc/qualcomm/common/display/mdss.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index 2d2821b..a2dda39 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <console/console.h> #include <edid.h> -#include <delay.h> #include <timer.h> #include <types.h> #include <string.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index eebb122..5074317 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <edid.h> #include <soc/clock.h> diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index b9fe87e..d5576f2 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -4,7 +4,6 @@ #include <soc/gpio.h> #include <stdint.h> #include <arch/mmio.h> -#include <delay.h> #include <assert.h> #include <device/mmio.h> #include <gpio.h> diff --git a/src/soc/sifive/fu740/spi.c b/src/soc/sifive/fu740/spi.c index 908e6ca..415ba85 100644 --- a/src/soc/sifive/fu740/spi.c +++ b/src/soc/sifive/fu740/spi.c @@ -6,7 +6,6 @@ #include <soc/spi.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <delay.h> #include <lib.h> #include "spi_internal.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/81812?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Gerrit-Change-Number: 81812 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: tree: Drop unused <console/console.h>
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81811?usp=email ) Change subject: tree: Drop unused <console/console.h> ...................................................................... tree: Drop unused <console/console.h> Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/breakpoint.c M src/drivers/smmstore/ramstage.c M src/drivers/spi/issi.c M src/mainboard/bytedance/bd_egs/romstage.c M src/mainboard/emulation/qemu-riscv/cbmem.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/brya/variants/constitution/variant.c M src/mainboard/google/corsola/panel.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/geralt/panel_geralt.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/herobrine/boardid.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/myst/mainboard.c M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/rex/variants/ovis/gpio.c M src/mainboard/google/rex/variants/rex0/gpio.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/skyrim/variants/baseboard/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c M src/mainboard/msi/ms7e06/romstage_fsp_params.c M src/mainboard/purism/librem_jsl/bootblock.c M src/mainboard/purism/librem_jsl/romstage.c M src/mainboard/purism/librem_l1um_v2/romstage.c M src/mainboard/starlabs/lite/bootblock.c M src/mainboard/starlabs/lite/smbios.c M src/mainboard/starlabs/starbook/variants/kbl/romstage.c M src/northbridge/intel/haswell/early_pcie.c M src/northbridge/intel/sandybridge/common.c M src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/genoa_poc/i2c.c M src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/meteorlake/pcie_rp.c M src/soc/intel/meteorlake/soc_info.c M src/soc/intel/xeon_sp/pch.c M src/soc/intel/xeon_sp/pmc.c M src/soc/intel/xeon_sp/pmutil.c M src/soc/mediatek/common/bl31.c M src/soc/mediatek/common/devapc.c M src/soc/mediatek/common/msdc.c M src/soc/mediatek/mt8186/pmif_spmi.c M src/soc/mediatek/mt8188/lastbus.c M src/soc/mediatek/mt8195/pcie.c M src/soc/sifive/fu740/clock.c M src/soc/sifive/fu740/gpio.c 55 files changed, 0 insertions(+), 55 deletions(-) Approvals: build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve Jonathon Hall: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved diff --git a/src/arch/x86/breakpoint.c b/src/arch/x86/breakpoint.c index d3ba783..be9359f 100644 --- a/src/arch/x86/breakpoint.c +++ b/src/arch/x86/breakpoint.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/registers.h> #include <arch/breakpoint.h> -#include <console/console.h> #include <types.h> #define DEBUG_REGISTER_COUNT 4 diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index e897aa2..857fe89 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -4,7 +4,6 @@ #include <cpu/x86/smm.h> #include <commonlib/helpers.h> #include <commonlib/region.h> -#include <console/console.h> #include <smm_call.h> #include <smmstore.h> #include <types.h> diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c index d2000b9..884fcdb 100644 --- a/src/drivers/spi/issi.c +++ b/src/drivers/spi/issi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c index f33e74e..e1e976b 100644 --- a/src/mainboard/bytedance/bd_egs/romstage.c +++ b/src/mainboard/bytedance/bd_egs/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c index 10ca2cd..e4d21cc 100644 --- a/src/mainboard/emulation/qemu-riscv/cbmem.c +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -3,7 +3,6 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> -#include <console/console.h> uintptr_t cbmem_top_chipset(void) { diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 9f86abe..e20976c 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/brya/variants/constitution/variant.c b/src/mainboard/google/brya/variants/constitution/variant.c index 289481c..ca09253 100644 --- a/src/mainboard/google/brya/variants/constitution/variant.c +++ b/src/mainboard/google/brya/variants/constitution/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <fw_config.h> #include <sar.h> diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c index 0eb9420..01eb243 100644 --- a/src/mainboard/google/corsola/panel.c +++ b/src/mainboard/google/corsola/panel.c @@ -2,7 +2,6 @@ #include <boardid.h> #include <cbfs.h> -#include <console/console.h> #include <device/i2c_simple.h> #include <edid.h> #include <gpio.h> diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 944d033..d0af1d4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <device/mmio.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 0b59a4e..cd6dbe9 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/i2c.h> #include "gpio.h" diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index b1adb86..744d5d1 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variant.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <gpio.h> diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 18d5e8f..49a80e7 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -8,7 +8,6 @@ #include <amdblocks/psp.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c index 38aeb20..79ed15a 100644 --- a/src/mainboard/google/herobrine/boardid.c +++ b/src/mainboard/google/herobrine/boardid.c @@ -4,7 +4,6 @@ #include <ec/google/chromeec/ec.h> #include "board.h" #include <commonlib/bsd/cb_err.h> -#include <console/console.h> #include <gpio.h> #include <soc/socinfo.h> diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 54666da..076d3fe 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 81972ff..b75bd4a 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index e5d2858..57bfcd4 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -5,7 +5,6 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 664b440..323f039 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 6f652ed..30f704c 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c index f188929..5624df9 100644 --- a/src/mainboard/google/rex/variants/ovis/gpio.c +++ b/src/mainboard/google/rex/variants/ovis/gpio.c @@ -10,7 +10,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> -#include <console/console.h> #include <boardid.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 4ccf327..9d8f9ff 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -10,7 +10,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> -#include <console/console.h> #include <boardid.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c index f265cbf..060119d 100644 --- a/src/mainboard/google/skyrim/ec.c +++ b/src/mainboard/google/skyrim/ec.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <amdblocks/smi.h> -#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/smi.h> diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 8a395a8..5925f29 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -6,7 +6,6 @@ #include <amdblocks/psp.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c index ff59b2b..a14dc98 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c +++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 43c2bf4..cefaf7a 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 4e9524d..803056a 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 58c7dfb..b53d369 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index d592fdc..3f3a81b 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 3ced7f8..7f5ea85 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> diff --git a/src/mainboard/msi/ms7e06/romstage_fsp_params.c b/src/mainboard/msi/ms7e06/romstage_fsp_params.c index d3c3c50..6fa8dc3 100644 --- a/src/mainboard/msi/ms7e06/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7e06/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> diff --git a/src/mainboard/purism/librem_jsl/bootblock.c b/src/mainboard/purism/librem_jsl/bootblock.c index c629a6d..e97fc4d 100644 --- a/src/mainboard/purism/librem_jsl/bootblock.c +++ b/src/mainboard/purism/librem_jsl/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <delay.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/purism/librem_jsl/romstage.c b/src/mainboard/purism/librem_jsl/romstage.c index 65205ad..e516457 100644 --- a/src/mainboard/purism/librem_jsl/romstage.c +++ b/src/mainboard/purism/librem_jsl/romstage.c @@ -5,7 +5,6 @@ #include <soc/meminit.h> #include <soc/romstage.h> #include <device/pci_ops.h> -#include <console/console.h> static const struct mb_cfg board_mem_cfg = { .dq_map[DDR_CH0] = { diff --git a/src/mainboard/purism/librem_l1um_v2/romstage.c b/src/mainboard/purism/librem_l1um_v2/romstage.c index 6cceba3..666adc2 100644 --- a/src/mainboard/purism/librem_l1um_v2/romstage.c +++ b/src/mainboard/purism/librem_l1um_v2/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/starlabs/lite/bootblock.c b/src/mainboard/starlabs/lite/bootblock.c index 6bf1723..91e2e23 100644 --- a/src/mainboard/starlabs/lite/bootblock.c +++ b/src/mainboard/starlabs/lite/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <intelblocks/lpc_lib.h> #include <soc/gpio.h> #include <variants.h> diff --git a/src/mainboard/starlabs/lite/smbios.c b/src/mainboard/starlabs/lite/smbios.c index d9ae270..5b85f50 100644 --- a/src/mainboard/starlabs/lite/smbios.c +++ b/src/mainboard/starlabs/lite/smbios.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <ec/starlabs/merlin/ec.h> diff --git a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c index 72fe9ed..d1e928e 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <option.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c index d3940e3..3fc8713 100644 --- a/src/northbridge/intel/haswell/early_pcie.c +++ b/src/northbridge/intel/haswell/early_pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <device/pci_def.h> #include <device/pci_mmio_cfg.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index a670491..0ee7e1d 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 6a7ae13..7eeecb5 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <cpu/x86/tsc.h> #include <psp_verstage/psp_transfer.h> #include <symbols.h> diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index 8f842f9..fc22304 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -7,7 +7,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/cpu.h> #include <arch/ioapic.h> -#include <console/console.h> #include <device/device.h> #include <vendorcode/amd/opensil/genoa_poc/opensil.h> diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c index 7261a87..aac73f0 100644 --- a/src/soc/amd/genoa_poc/i2c.c +++ b/src/soc/amd/genoa_poc/i2c.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/i2c.h> -#include <console/console.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include "chip.h" diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c index 41b815b..769b853 100644 --- a/src/soc/intel/common/block/p2sb/ioe_p2sb.c +++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c @@ -2,7 +2,6 @@ #define __SIMPLE_DEVICE__ -#include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/p2sb.h> diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 04318c8..e348501 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -3,7 +3,6 @@ #define __SIMPLE_DEVICE__ #include <device/pci_ops.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 1b4045e..9f59ce1 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -4,7 +4,6 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/soc_info.h> -#include <console/console.h> static const struct pcie_rp_group mtlp_rp_groups[] = { { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 }, diff --git a/src/soc/intel/meteorlake/soc_info.c b/src/soc/intel/meteorlake/soc_info.c index 0772c7799..275d568 100644 --- a/src/soc/intel/meteorlake/soc_info.c +++ b/src/soc/intel/meteorlake/soc_info.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <soc/soc_info.h> #include <intelblocks/tcss.h> -#include <console/console.h> uint8_t get_max_usb20_port(void) { diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 23af6d9..5f480d6 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -9,7 +9,6 @@ #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pmc.h> -#include <console/console.h> void override_hpet_ioapic_bdf(void) { diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index 4321625..6a784e0 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> #include <intelblocks/pmc.h> diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 336e867..0d77a2a 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -7,7 +7,6 @@ #define __SIMPLE_DEVICE__ -#include <console/console.h> #include <device/pci.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/mediatek/common/bl31.c b/src/soc/mediatek/common/bl31.c index 6a79098..e6e5bbc 100644 --- a/src/soc/mediatek/common/bl31.c +++ b/src/soc/mediatek/common/bl31.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bl31.h> -#include <console/console.h> #include <gpio.h> #include <soc/bl31.h> diff --git a/src/soc/mediatek/common/devapc.c b/src/soc/mediatek/common/devapc.c index 7838d7d..5873dd5 100644 --- a/src/soc/mediatek/common/devapc.c +++ b/src/soc/mediatek/common/devapc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <console/console.h> #include <soc/devapc.h> #include <soc/devapc_common.h> diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c index e7cd571..df59b0e 100644 --- a/src/soc/mediatek/common/msdc.c +++ b/src/soc/mediatek/common/msdc.c @@ -5,7 +5,6 @@ #include <assert.h> #include <commonlib/bsd/helpers.h> #include <commonlib/storage/sd_mmc.h> -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <lib.h> diff --git a/src/soc/mediatek/mt8186/pmif_spmi.c b/src/soc/mediatek/mt8186/pmif_spmi.c index 28ea739..614985b 100644 --- a/src/soc/mediatek/mt8186/pmif_spmi.c +++ b/src/soc/mediatek/mt8186/pmif_spmi.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <soc/pll.h> #include <soc/pmif_spmi.h> -#include <console/console.h> /* IOCFG_LT, DRV_CFG2 */ DEFINE_BITFIELD(SPMI_SCL, 14, 12) diff --git a/src/soc/mediatek/mt8188/lastbus.c b/src/soc/mediatek/mt8188/lastbus.c index 5d117af..8bf6a87 100644 --- a/src/soc/mediatek/mt8188/lastbus.c +++ b/src/soc/mediatek/mt8188/lastbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/lastbus_v2.h> diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index cb36f8d..fa5bbd7 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <console/console.h> #include <device/mmio.h> #include <device/resource.h> #include <delay.h> diff --git a/src/soc/sifive/fu740/clock.c b/src/soc/sifive/fu740/clock.c index 419a0e2..91e7992 100644 --- a/src/soc/sifive/fu740/clock.c +++ b/src/soc/sifive/fu740/clock.c @@ -3,7 +3,6 @@ // This file is used for setting up clocks and get devices out of reset // For more Information see FU740-C000 Manual Chapter 7 Clocking and Reset -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/addressmap.h> diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index 167844d..b9fe87e 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/addressmap.h> #include <soc/gpio.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81811?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Gerrit-Change-Number: 81811 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger 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[XS] Change in coreboot[main]: mb/google/*: Drop unused header file console/console.h
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81685?usp=email ) Change subject: mb/google/*: Drop unused header file console/console.h ...................................................................... mb/google/*: Drop unused header file console/console.h The header file console/console.h is unused, just drop it. TEST=abuild -t google/corsola -b wugtrio -a TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/panel_wugtrio.c M src/mainboard/google/geralt/panel_ciri.c 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: cong yang: Looks good to me, but someone else must approve build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Yidi Lin: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c index 3405c0d..8d6919e 100644 --- a/src/mainboard/google/corsola/panel_wugtrio.c +++ b/src/mainboard/google/corsola/panel_wugtrio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <delay.h> #include <gpio.h> #include <soc/regulator.h> diff --git a/src/mainboard/google/geralt/panel_ciri.c b/src/mainboard/google/geralt/panel_ciri.c index 4d31711..15c8859 100644 --- a/src/mainboard/google/geralt/panel_ciri.c +++ b/src/mainboard/google/geralt/panel_ciri.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/i2c.h> #include <soc/regulator.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Gerrit-Change-Number: 81685 Gerrit-PatchSet: 2 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
by Shelley Chen (Code Review) 09 Apr '24

09 Apr '24

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81789?usp=email ) Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO ...................................................................... mb/google/brox: Initialize NOTE_BOOK_MODE GPIO The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. This CL accounts for those changes. BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change. Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81789/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 337fde1..fba75b2 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -115,7 +115,7 @@ /* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */ /* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */ PAD_NC(GPP_B16, NONE), - /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> NOTE_BOOK_MODE (NC initially) */ + /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> ISH_I2C_EC_SCL (NC) */ PAD_NC(GPP_B17, NONE), /* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), @@ -198,8 +198,8 @@ PAD_NC(GPP_E7, NONE), /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> SOC_GPP_E9 (NC) */ - PAD_NC(GPP_E9, NONE), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_GPO(GPP_E9, 0, PLTRST), /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ PAD_CFG_GPI(GPP_E10, NONE, PLTRST), /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> SOC_GPP_E11 (NC) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Gerrit-Change-Number: 81789 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: security/tpm: support compiling in multiple TPM drivers
by Sergii Dmytruk (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162?usp=email ) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... Patch Set 37: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69162/comment/e56ef959_68e05afe : PS31, Line 14: Makefile.inc files were updated to replace `all-*` with romstage, > And here are 132 failures caused by including what's not being used: https://qa.coreboot. […] Finally figured out where my scary-looking condition got it wrong and now CI passes without excluding TPM drivers from any stages. File src/drivers/i2c/tpm/Makefile.mk: https://review.coreboot.org/c/coreboot/+/69162/comment/d1e6a79d_51977160 : PS31, Line 5: romstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c : ramstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c : verstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c : : romstage-$(CONFIG_TPM_ATMEL) += tis_atmel.c : ramstage-$(CONFIG_TPM_ATMEL) += tis_atmel.c : verstage-$(CONFIG_TPM_ATMEL) += tis_atmel.c : : ifeq ($(CONFIG_TPM_GOOGLE),y) : : romstage-y += cr50.c : ramstage-y += cr50.c : verstage-y += cr50.c : else : : romstage-y += tpm.c : ramstage-y += tpm.c : verstage-y += tpm.c : > So now these files will no longer be compiled for postcar, but postcar may want to measure the ramst […] Changes to Makefiles were dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/69162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 37 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Apr 2024 21:50:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: security/tpm: support compiling in multiple TPM drivers
by Sergii Dmytruk (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Raul Rangel, Sergii Dmytruk. Hello Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69162?usp=email to look at the new patch set (#37). Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... security/tpm: support compiling in multiple TPM drivers Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/lib/program.ld M src/security/tpm/Kconfig M src/security/tpm/tis.h M src/security/tpm/tss/tss.c M src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld 10 files changed, 62 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69162/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/69162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 37 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: buildgcc: Match the string of downloading percentage more precisely
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Bao Zheng, Felix Singer, Martin L Roth, Zheng Bao. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66743?usp=email ) Change subject: buildgcc: Match the string of downloading percentage more precisely ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ef9e7c87fd4ee6cc707346954d91e6e3af3b939 Gerrit-Change-Number: 66743 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 09 Apr 2024 20:29:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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