coreboot-gerrit April 2024

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[S] Change in libgfxinit[main]: gfxtest: Fix out-of-order components, permanently
by Elyes Haouas (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/81854?usp=email ) Change subject: gfxtest: Fix out-of-order components, permanently ...................................................................... Patch Set 1: (1 comment) File gfxtest/hw-gfx-gma-gfx_test.adb: https://review.coreboot.org/c/libgfxinit/+/81854/comment/6dff8e60_f9e133f6 : PS1, Line 54: Blue : Byte; : Green : Byte; : Red : Byte; I would keep using the RGB order That is the order in color space (see http://cie.co.at ) -- To view, visit https://review.coreboot.org/c/libgfxinit/+/81854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I77dbdcd6c235e411585585779c31777adcef57d0 Gerrit-Change-Number: 81854 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 15:01:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Martin L Roth, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81785?usp=email ) Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 81785 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 15:00:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Add support for TPM1.2 device
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Máté Kukri. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81827?usp=email ) Change subject: mb/dell/optiplex_9020: Add support for TPM1.2 device ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec05321862aed58695c256b00494e5953219786d Gerrit-Change-Number: 81827 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 14:59:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/inteltool: Add more Westmere/Ironlake device IDs
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Felix Singer, Pratikkumar V Prajapati. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60215?usp=email ) Change subject: util/inteltool: Add more Westmere/Ironlake device IDs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60215/comment/e52f3431_ce86b4dc : PS2, Line 8: > CB:45562 explains where the IDs come from Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Gerrit-Change-Number: 60215 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 14:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/inteltool: Add more Westmere/Ironlake device IDs
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Angel Pons, Felix Singer. Hello Felix Held, Felix Singer, Michael Niewöhner, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60215?usp=email to look at the new patch set (#3). Change subject: util/inteltool: Add more Westmere/Ironlake device IDs ...................................................................... util/inteltool: Add more Westmere/Ironlake device IDs The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. For the sake of completeness, add the PCI device IDs for Clarkdale. Though coreboot only supports Arrandale, both of them are Ironlake. It is possible that the Management Engine handles changing the PCI device ID, which would not happen when using a broken ME firmware. Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/60215/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Gerrit-Change-Number: 60215 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: tree: Drop duplicated <stdarg.h> and <stdio.h>
by Elyes Haouas (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jakub Czapiga, Johnny Lin, Jérémy Compostella, Tim Chu. Hello Arthur Heymans, Christian Walter, Jakub Czapiga, Johnny Lin, Jérémy Compostella, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81853?usp=email to look at the new patch set (#2). Change subject: tree: Drop duplicated <stdarg.h> and <stdio.h> ...................................................................... tree: Drop duplicated <stdarg.h> and <stdio.h> <string.h> is supposed to provide <stdarg.h> and <stdio.h> Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/console/vsprintf.c M src/console/vtxprintf.c M src/cpu/x86/smm/smm_module_loader.c M src/device/pci_rom.c M src/drivers/ocp/dmi/smbios.c M src/mainboard/ocp/deltalake/ramstage.c M tests/lib/string-test.c 7 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/81853/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2 Gerrit-Change-Number: 81853 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in libgfxinit[master]: Add Bay Trail options
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44790 ) Change subject: Add Bay Trail options ...................................................................... Add Bay Trail options This will build the G45 code, though. Actual Bay Trail code will be added in subsequent commits. Change-Id: Ib30ea668da9641ccf1f94f8f25cfb897faa54aaa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma-panel.adb M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads A common/valleyview/Makefile.inc A configs/baytrail 10 files changed, 154 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/90/44790/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index f2a2fbb..8935dda 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -57,13 +57,14 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)) CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS := $(if $(filter y,$(CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS)),True,False) -_GEN_TLA_SUBSTITUTIONS := $g45\|ilk\|hsw\|skl$ +_GEN_TLA_SUBSTITUTIONS := $g45\|vlv\|ilk\|hsw\|skl$ _GEN_NONCONST := $(strip \ $(if $(filter G45,$(CONFIG_GFX_GMA_GENERATION)),g45, \ + $(if $(filter Valleyview,$(CONFIG_GFX_GMA_GENERATION)),vlv, \ $(if $(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),ilk, \ $(if $(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),hsw, \ - $(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl))))) + $(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl)))))) # GNATprove (GPL 2017) doesn't realize when a boolean expression # that depends both on static values and variables can be evalu- # ated at compile time (e.g. `False and then Variable` is always @@ -113,6 +114,8 @@ ifneq ($(filter G45,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += g45 +else ifneq ($(filter Valleyview,$(CONFIG_GFX_GMA_GENERATION)),) +subdirs-y += valleyview else ifneq ($(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += ironlake else ifneq ($(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),) diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index a39ecd9..b260e76 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -20,18 +20,20 @@ CPU_First : constant CPU_Type := (case Gen is - when G45 => G45, - when Ironlake => Ironlake, - when Haswell => Haswell, - when Broxton => Broxton, - when Skylake => Skylake); + when G45 => G45, + when Valleyview => Baytrail, + when Ironlake => Ironlake, + when Haswell => Haswell, + when Broxton => Broxton, + when Skylake => Skylake); CPU_Last : constant CPU_Type := (case Gen is - when G45 => GM45, - when Ironlake => Ivybridge, - when Haswell => Broadwell, - when Broxton => Broxton, - when Skylake => Kabylake); + when G45 => GM45, + when Valleyview => Baytrail, + when Ironlake => Ivybridge, + when Haswell => Broadwell, + when Broxton => Broxton, + when Skylake => Kabylake); CPU_Var_Last : constant CPU_Variant := (case Gen is when Haswell | Skylake => ULX, @@ -118,6 +120,7 @@ -- values start after a line break. Gen_G45 : <genbool> := Gen = G45; + Gen_Valleyview : <genbool> := Gen = Valleyview; Gen_Ironlake : <genbool> := Gen = Ironlake; Gen_Haswell : <genbool> := Gen = Haswell; Gen_Broxton : <genbool> := Gen = Broxton; @@ -160,8 +163,9 @@ Is_LP : <hswsklbool> := Is_ULT or Is_ULX; ---------- CPU pipe: --------- - Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; - Disable_Trickle_Feed : <genbool> := not Gen_Haswell; + Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; -- VLV: False -- c.f. EDS or similar +-- Disable_Trickle_Feed : <genbool> := not Gen_Haswell; -- VLV: True -- intel_display_power.c: vlv_init_display_clock_gating() + Disable_Trickle_Feed : <genbool> := not Gen_Haswell and not Gen_Valleyview; -- VLV: False -- wise icon says: intel_display.c: i9xx_plane_ctl() conditions around 'DISPPLANE_TRICKLE_FEED_DISABLE' Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell; Has_EDP_Transcoder : <genbool> := Haswell_On; Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell; @@ -176,9 +180,15 @@ Has_Ivybridge_Cursors : <ilkbool> := Ivybridge_On; VGA_Plane_Workaround : <ilkbool> := CPU_Ivybridge; Has_GMCH_DP_Transcoder : <genbool> := Gen_G45; - Has_GMCH_VGACNTRL : <genbool> := Gen_G45; - Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45; + Has_GMCH_VGACNTRL : <genbool> := Gen_G45 or Gen_Valleyview; + Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45 or Gen_Valleyview; + -- wise icon checks bay trail and says: + -- + -- Looks like there are two sets of PP controls and they are tied to the + -- chosen display pipe (instead of the set of physical pins as usual). + -- This will screw us eventually, but nothing to worry about now. + -- --------- Panel power: ------- Has_PP_Write_Protection : <genbool> := Up_To_Ironlake; Has_PP_Port_Select : <genbool> := Up_To_Ironlake; @@ -188,7 +198,7 @@ Has_New_Backlight_Control : <genbool> := Gen_Broxton; ----------- PCH/FDI: --------- - Has_PCH : <genbool> := not Gen_Broxton and not Gen_G45; + Has_PCH : <genbool> := not (Gen_Broxton or Gen_Valleyview or Gen_G45); Has_PCH_DAC : <hswbool> := (Gen_Ironlake or (Gen_Haswell and then not Is_LP)); @@ -209,7 +219,7 @@ Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell; ---------- Clocks: ----------- - Has_GMCH_RawClk : <genbool> := Gen_G45; + Has_GMCH_RawClk : <genbool> := Gen_G45 or Gen_Valleyview; Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45; Has_Broadwell_CDClk : <hswbool> := CPU_Broadwell; Can_Switch_CDClk : <hswbool> := Broadwell_On; @@ -298,6 +308,7 @@ Default_CDClk_Freq : <ilkhswvar> CDClk_Range := (if Gen_G45 then 320_000_000 -- unused + elsif Gen_Valleyview then 320_000_000 -- runtime configurable elsif CPU_Ironlake then 450_000_000 elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000 elsif Gen_Haswell and then Is_ULX then 337_500_000 @@ -308,6 +319,7 @@ Default_RawClk_Freq : <hswvar> Frequency_Type := (if Gen_G45 then 100_000_000 -- unused, depends on FSB + elsif Gen_Valleyview then 100_000_000 -- not constant, must be looked at runtime elsif Gen_Ironlake then 125_000_000 elsif Gen_Haswell then (if Is_LP then 24_000_000 else 125_000_000) elsif Gen_Broxton then Frequency_Type'First -- none needed @@ -326,7 +338,7 @@ (Primary => 4096, Secondary => 2048, Tertiary => Pos32'First) - elsif Gen_Ironlake or CPU_Haswell then + elsif Gen_Valleyview or Gen_Ironlake or CPU_Haswell then (Primary => 4096, Secondary => 2048, Tertiary => 2048) @@ -349,12 +361,12 @@ HDMI_Max_Clock_24bpp : constant Frequency_Type := (case Gen is when Generation'First .. G45 => 165_000_000, - when Ironlake => 225_000_000, + when Valleyview .. Ironlake => 225_000_000, when Haswell .. Generation'Last => 300_000_000); ---------------------------------------------------------------------------- - Display_Base_Offset : constant := 0; + Display_Base_Offset : constant := (if Gen_Valleyview then 16#18_0000# else 0); GTT_PTE_Size : <hswvar> Natural := (if Has_64bit_GTT then 8 else 4); @@ -379,6 +391,10 @@ -- From Haswell on, we have to distinguish between -- Normal, ULT (U CPU lines) and ULX (Y CPU lines). + function Is_Baytrail (Device_Id : Word16) return Boolean is -- VLV: i915_pciids.h: INTEL_VLV_IDS + ((Device_Id and 16#fffc#) = 16#0f30# or + (Device_Id and 16#fffd#) = 16#0155#); + function Is_Haswell_Y (Device_Id : Word16) return Boolean is ((Device_Id and 16#ffef#) = 16#0a0e#); function Is_Haswell_U (Device_Id : Word16) return Boolean is @@ -450,6 +466,7 @@ (case CPU is when G45 => (Device_Id and 16#ff02#) = 16#2e02#, when GM45 => (Device_Id and 16#fffe#) = 16#2a42#, + when Baytrail => Is_Baytrail (Device_Id), when Ironlake => (Device_Id and 16#fff3#) = 16#0042#, when Sandybridge => (Device_Id and 16#ffc2#) = 16#0102#, when Ivybridge => (Device_Id and 16#ffc3#) = 16#0142#, diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb index 2a09305..4141e15 100644 --- a/common/hw-gfx-gma-config_helpers.adb +++ b/common/hw-gfx-gma-config_helpers.adb @@ -29,7 +29,7 @@ begin return (case Config.Gen is - when G45 => -- everything on GMCH + when G45 | Valleyview => -- everything on GMCH or SoC (case Port is when LVDS => LVDS, when eDP => DIGI_A, -- n/a, actually diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index e343deb..e5670ae 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -114,12 +114,18 @@ DIVISOR => Registers.PCH_PP_DIVISOR)) -- won't be used else - (Panel_1 .. Panel_2 => + (Panel_1 => (STATUS => Registers.GMCH_PP_STATUS, CONTROL => Registers.GMCH_PP_CONTROL, ON_DELAYS => Registers.GMCH_PP_ON_DELAYS, OFF_DELAYS => Registers.GMCH_PP_OFF_DELAYS, - DIVISOR => Registers.GMCH_PP_DIVISOR))); + DIVISOR => Registers.GMCH_PP_DIVISOR), + Panel_2 => + (STATUS => Registers.VLV_PIPE_B_PP_STATUS, + CONTROL => Registers.VLV_PIPE_B_PP_CONTROL, + ON_DELAYS => Registers.VLV_PIPE_B_PP_ON_DLY, + OFF_DELAYS => Registers.VLV_PIPE_B_PP_OFF_DLY, + DIVISOR => Registers.VLV_PIPE_B_PP_DIVISOR))); function PCH_PP_ON_DELAYS_PWR_UP (US : Natural) return Word32 is begin @@ -256,11 +262,14 @@ end if; if Override_Delays then - if Config.Has_PP_Port_Select then + if Config.Gen_Valleyview then + Port_Select := PCH_PP_ON_DELAYS_PORT_SELECT_DP_C; + elsif Config.Has_PP_Port_Select then Port_Select := (case Config.Panel_Ports (Panel_1) is when LVDS => PCH_PP_ON_DELAYS_PORT_SELECT_LVDS, when eDP => PCH_PP_ON_DELAYS_PORT_SELECT_DP_A, + when DP1 | HDMI1 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_A, -- FIXME: VLV HACK when DP2 | HDMI2 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_C, when DP3 | HDMI3 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_D, when others => 0); diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 641f192..66d16e8 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -252,15 +252,18 @@ ---------------------------------------------------------------------------- -- Write a specific register - procedure Write (Register : Registers_Index; Value : Word32) + procedure Write + (Register : Registers_Index; + Value : Word32; + Verbose : Boolean := True) is begin - pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); - pragma Debug (Debug.Put_Word32 (Value)); - pragma Debug (Debug.Put (" -> ")); - pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); - pragma Debug (Debug.Put (":")); - pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); + pragma Debug (Verbose, Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); + pragma Debug (Verbose, Debug.Put_Word32 (Value)); + pragma Debug (Verbose, Debug.Put (" -> ")); + pragma Debug (Verbose, Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); + pragma Debug (Verbose, Debug.Put (":")); + pragma Debug (Verbose, Debug.Put_Line (Registers_Index'Image (Register))); Regs.Write (Rep.Index (Register), Value); pragma Debug (Debug.Register_Write_Wait); @@ -289,7 +292,7 @@ pragma Warnings (GNATprove, Off, "unused assignment to ""Ignored_Success"""); -- Wait for the bits in @Register@ indicated by @Mask@ to be of @Value@ - procedure Wait + procedure Wait_Quietly (Register : in Registers_Index; Mask : in Word32; Value : in Word32; @@ -301,14 +304,6 @@ Timeout : Time.T; Timed_Out : Boolean := False; begin - pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); - pragma Debug (Debug.Put_Word32 (Value)); - pragma Debug (Debug.Put (" <- ")); - pragma Debug (Debug.Put_Word32 (Mask)); - pragma Debug (Debug.Put (" & ")); - pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); - pragma Debug (Debug.Put (":")); - pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); Timeout := Time.MS_From_Now (TOut_MS); loop @@ -318,14 +313,36 @@ Timed_Out := False; exit; end if; - pragma Debug (Timed_Out, Debug.Put (GNAT.Source_Info.Enclosing_Entity)); - pragma Debug (Timed_Out, Debug.Put_Line (": Timed Out!")); exit when Timed_Out; Timed_Out := Time.Timed_Out (Timeout); end loop; Success := not Timed_Out; + end Wait_Quietly; + + procedure Wait + (Register : in Registers_Index; + Mask : in Word32; + Value : in Word32; + TOut_MS : in Natural := Default_Timeout_MS; + Verbose : in Boolean := False; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); + pragma Debug (Debug.Put_Word32 (Value)); + pragma Debug (Debug.Put (" <- ")); + pragma Debug (Debug.Put_Word32 (Mask)); + pragma Debug (Debug.Put (" & ")); + pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); + pragma Debug (Debug.Put (":")); + pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); + + Wait_Quietly (Register, Mask, Value, TOut_MS, Verbose, Success); + + pragma Debug (not Success, Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (not Success, Debug.Put_Line (": Timed Out!")); end Wait; procedure Wait diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 68e5664..b158300 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -46,6 +46,10 @@ MI_MODE, INSTPM, GT_MODE, + VLV_IOSF_DOORBELL_REQ, + VLV_IOSF_DATA, + VLV_IOSF_ADDR, + VLV_DPIO_CTL, CACHE_MODE_0, CTX_SIZE, PP_DCLV_HIGH, @@ -188,6 +192,11 @@ GMCH_PP_OFF_DELAYS, GMCH_PP_DIVISOR, GMCH_PFIT_CONTROL, + VLV_PIPE_B_PP_STATUS, + VLV_PIPE_B_PP_CONTROL, + VLV_PIPE_B_PP_ON_DLY, + VLV_PIPE_B_PP_OFF_DLY, + VLV_PIPE_B_PP_DIVISOR, PIPEB_DDI_FUNC_CTL, PIPEB_MSA_MISC, SRD_CTL_B, @@ -757,7 +766,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A + ); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -772,6 +782,16 @@ (Invalid_Register => 0, --------------------------------------------------------------------------- + -- Valleyview registers + --------------------------------------------------------------------------- + + VLV_IOSF_DOORBELL_REQ => 16#00_2100# / Register_Width, + VLV_IOSF_DATA => 16#00_2104# / Register_Width, + VLV_IOSF_ADDR => 16#00_2108# / Register_Width, + + VLV_DPIO_CTL => 16#00_2110# / Register_Width, + + --------------------------------------------------------------------------- -- Pipe A registers --------------------------------------------------------------------------- @@ -800,8 +820,8 @@ PIPEA_DATA_N1 => 16#06_0034# / Register_Width, PIPEA_LINK_M1 => 16#06_0040# / Register_Width, PIPEA_LINK_N1 => 16#06_0044# / Register_Width, - PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width, - PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width, + PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width, -- aliased by VLV_DDL1 + PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width, -- aliased by VLV_DDL2 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width, PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width, PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width, @@ -1436,6 +1456,11 @@ GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width, GMCH_PP_DIVISOR => 16#06_1210# / Register_Width, GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width, + VLV_PIPE_B_PP_STATUS => 16#06_1300# / Register_Width, + VLV_PIPE_B_PP_CONTROL => 16#06_1304# / Register_Width, + VLV_PIPE_B_PP_ON_DLY => 16#06_1308# / Register_Width, + VLV_PIPE_B_PP_OFF_DLY => 16#06_130c# / Register_Width, + VLV_PIPE_B_PP_DIVISOR => 16#06_1310# / Register_Width, PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1 @@ -1668,6 +1693,8 @@ GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B; GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB; GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC; + VLV_DDL1 : constant Registers_Index := PIPEA_GMCH_DATA_M; + VLV_DDL2 : constant Registers_Index := PIPEA_GMCH_DATA_N; CURACNTR : constant Registers_Index := CUR_CTL_A; CURABASE : constant Registers_Index := CUR_BASE_A; CURAPOS : constant Registers_Index := CUR_POS_A; @@ -1704,10 +1731,11 @@ procedure Write (Register : Registers_Index; - Value : Word32) + Value : Word32; + Verbose : Boolean := True) with Global => (In_Out => Register_State), - Depends => (Register_State => (Register, Register_State, Value)), + Depends => (Register_State => (Register, Register_State, Value), null => Verbose), Pre => True, Post => True; @@ -1718,6 +1746,14 @@ pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""", Reason => "Only used on debugging path"); + + procedure Wait_Quietly + (Register : in Registers_Index; + Mask : in Word32; + Value : in Word32; + TOut_MS : in Natural := Default_Timeout_MS; + Verbose : in Boolean := False; + Success : out Boolean); procedure Wait (Register : in Registers_Index; Mask : in Word32; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..a363738 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -422,7 +422,7 @@ Audio_VID_DID : Word32; begin case Config.Gen is - when G45 => + when G45 .. Valleyview => Registers.Read (Registers.G4X_AUD_VID_DID, Audio_VID_DID); when Ironlake => Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1215fc5..d7f7ab8 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -33,11 +33,12 @@ subtype GTT_Range is Natural range 0 .. 16#8_0000# - 1; GTT_Rotation_Offset : constant GTT_Range := GTT_Range'Last / 2 + 1; - type Generation is (G45, Ironlake, Haswell, Broxton, Skylake); + type Generation is (G45, Valleyview, Ironlake, Haswell, Broxton, Skylake); type CPU_Type is (G45, GM45, + Baytrail, Ironlake, Sandybridge, Ivybridge, diff --git a/common/valleyview/Makefile.inc b/common/valleyview/Makefile.inc new file mode 100644 index 0000000..766ade0 --- /dev/null +++ b/common/valleyview/Makefile.inc @@ -0,0 +1,15 @@ +gfxinit-y += ../g45/hw-gfx-gma-connectors.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-dp.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-dp.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-hdmi.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-hdmi.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-lvds.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-lvds.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.ads +gfxinit-y += ../g45/hw-gfx-gma-plls.adb +gfxinit-y += ../g45/hw-gfx-gma-plls.ads +gfxinit-y += ../g45/hw-gfx-gma-port_detect.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch.ads +gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.ads +gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.adb diff --git a/configs/baytrail b/configs/baytrail new file mode 100644 index 0000000..9df28fd --- /dev/null +++ b/configs/baytrail @@ -0,0 +1,6 @@ +CONFIG_GFX_GMA_DYN_CPU = y +CONFIG_GFX_GMA_GENERATION = Valleyview +CONFIG_GFX_GMA_PANEL_1_PORT = DP1 +CONFIG_GFX_GMA_PANEL_2_PORT = DP2 +CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC +CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ib30ea668da9641ccf1f94f8f25cfb897faa54aaa Gerrit-Change-Number: 44790 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 15

Change in libgfxinit[master]: gma: Use a full `case` statement in Decode_Stolen
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44934 ) Change subject: gma: Use a full `case` statement in Decode_Stolen ...................................................................... gma: Use a full `case` statement in Decode_Stolen Hopefully, this will cause a `missing case` warning when adding support for a new platform, instead of silently using the wrong functions. Change-Id: I39f37e931977f4f437b619188436c37752f6b915 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-gma.adb 1 file changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/34/44934/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..f36470e 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -739,20 +739,19 @@ GGC : Word16; begin Dev.Read16 (GGC, GGC_Reg); - if Config.Gen_G45 or Config.CPU_Ironlake then - GTT_Size := GTT_Size_Gen4 (GGC); - Stolen_Size := Stolen_Size_Gen4 (GGC); - elsif Config.CPU_Sandybridge or Config.CPU_Ivybridge or Config.CPU_Haswell - then - GTT_Size := GTT_Size_Gen6 (GGC); - Stolen_Size := Stolen_Size_Gen6 (GGC); - elsif Config.CPU_Broadwell then - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen8 (GGC); - else - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen9 (GGC); - end if; + + -- Upcasting is necessary to cover all cases + GTT_Size := + (case CPU_Type (Config.CPU) is + when G45 .. Ironlake => GTT_Size_Gen4 (GGC), + when Sandybridge .. Haswell => GTT_Size_Gen6 (GGC), + when Broadwell .. Kabylake => GTT_Size_Gen8 (GGC)); + Stolen_Size := + (case CPU_Type (Config.CPU) is + when G45 .. Ironlake => Stolen_Size_Gen4 (GGC), + when Sandybridge .. Haswell => Stolen_Size_Gen6 (GGC), + when Broadwell => Stolen_Size_Gen8 (GGC), + when Broxton .. Kabylake => Stolen_Size_Gen9 (GGC)); end Decode_Stolen; -- Additional runtime validation that FB fits stolen memory and aperture. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I39f37e931977f4f437b619188436c37752f6b915 Gerrit-Change-Number: 44934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in libgfxinit[master]: gma registers: Allow to specify an offset for display registers
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44786 ) Change subject: gma registers: Allow to specify an offset for display registers ...................................................................... gma registers: Allow to specify an offset for display registers Certain platforms, namely Bay Trail and Braswell, have the display engine registers at an offset relative to GTTMMADR base. Apart from that, the registers are rather similar to the ones on GMCH platforms. Allow platforms to specify at which offset within GTTMM the display registers are located. Use zero for all currently-supported platforms. Change-Id: Id5497a23776e9aa9e2fd5ca0479030cb8e55712f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.adb 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/86/44786/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 241fe8e..ecbd908 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -55,6 +55,8 @@ Default_MMIO_Base : constant := <<DEFAULT_MMIO_BASE>>; + Display_Base_Offset : constant := 0; + LVDS_Dual_Threshold : constant := 95_000_000; Ignore_Presence_Straps : constant Boolean := <<IGNORE_STRAPS>>; diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 3f0d7ae..5ea134a 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -211,7 +211,7 @@ SPARK_Mode => Off is begin - return Reg'Enum_Rep; + return Reg'Enum_Rep + Config.Display_Base_Offset; end Index; end Rep; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id5497a23776e9aa9e2fd5ca0479030cb8e55712f Gerrit-Change-Number: 44786 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 18

[XS] Change in coreboot[main]: mb/google/corsola: Add new board variant Skitty
by Herbert Wu (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Geoffrey Chien, Hung-Te Lin, Shawn Ku, Shawn Ku, Yidi Lin, Yu-Ping Wu. Herbert Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81772?usp=email ) Change subject: mb/google/corsola: Add new board variant Skitty ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15 Gerrit-Change-Number: 81772 Gerrit-PatchSet: 8 Gerrit-Owner: Herbert Wu <herbert1_wu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Geoffrey Chien <geoffrey_chien(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Herbert Wu <herbert1_wu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Geoffrey Chien <geoffrey_chien(a)pegatron.corp-partner.google.com> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Shawn Ku <shawnku(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 14:11:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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