coreboot-gerrit April 2024

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[S] Change in coreboot[main]: [RFC] PCI: Introduce `enable_mmconf()` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57046?usp=email ) Change subject: [RFC] PCI: Introduce `enable_mmconf()` function ...................................................................... Abandoned No interest in pursuing this -- To view, visit https://review.coreboot.org/c/coreboot/+/57046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f573f1c0d9a4cc3c25fe907d12778cd5d93241d Gerrit-Change-Number: 57046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49169 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function ...................................................................... [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function It was being run twice, in both bootblock and romstage. Using Lynxpoint as a reference, reorder the code so that it is only run once. Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 37 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49169/1 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..f594a9f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,8 +3,15 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <types.h> + #include "pch.h" +static void map_rcba(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +} + static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -33,13 +40,14 @@ void bootblock_early_southbridge_init(void) { + map_rcba(); enable_spi_prefetching_and_caching(); - - early_pch_init(); - enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc_decode(); + mainboard_pch_lpc_setup(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6daafe0..f684a96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -216,26 +216,6 @@ write_iobp(0xec000780, 0x02000020); } -static void pch_enable_bars(void) -{ - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - - /* Enable GPIO functionality. */ - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -} - -static void pch_generic_setup(void) -{ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ -} - static void pch_enable_gbe(void) { uint8_t wanted_buc; @@ -260,7 +240,27 @@ } } -static void pch_enable_lpc_decode(void) +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void pch_enable_lpc_decode(void) { /* * Enable some common LPC IO ranges: @@ -298,18 +298,13 @@ void early_pch_init(void) { - pch_enable_lpc_decode(); - - mainboard_pch_lpc_setup(); + pch_enable_gbe(); pch_enable_bars(); - pch_generic_setup(); - - pch_enable_gbe(); - setup_pch_gpios(&mainboard_gpio_map); - if (ENV_ROMSTAGE) - enable_smbus(); + pch_generic_setup(); + + enable_smbus(); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index dcab839..3b91e31 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,6 +56,7 @@ /* Optional mainboard hook to do additional LPC configuration or to override what is set up by default. */ void mainboard_pch_lpc_setup(void); +void pch_enable_lpc_decode(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Gerrit-Change-Number: 49169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49178 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic ...................................................................... [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic The initial steps came out of trace output from a Panther Point system. Add missing Cougar Point steps, and guard Panther Point specific steps. Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 33 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/49178/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0b60d13..e86297b 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -156,7 +156,10 @@ pch_iobp_update(0xeb0040a1, ~(0x3ff << 3), 0x9f << 3); pch_iobp_update(0xec0040a1, ~(0x3ff << 3), 0x9f << 3); - /* Some CPT-only writes go here */ + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec004086, ~0, 1 << 30); + pch_iobp_update(0xec004086, ~0, 1 << 31); + } pch_iobp_update(0xea004001, ~(3 << 10), 1 << 10); pch_iobp_update(0xeb004002, ~0, 1 << 30 | 1 << 21); @@ -189,34 +192,35 @@ /* PPT A0 resume-only xHCI workaround goes here */ - /* TODO: This section is PPT-only */ - pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); - pch_iobp_update(0xec000084, ~(1 << 31), 0); - pch_iobp_update(0xec000184, ~(1 << 31), 0); - pch_iobp_update(0xec000284, ~(1 << 31), 0); - pch_iobp_update(0xec000384, ~(1 << 31), 0); - pch_iobp_update(0xec000094, ~0, 0xf << 16); - pch_iobp_update(0xec000194, ~0, 0xf << 16); - pch_iobp_update(0xec000294, ~0, 0xf << 16); - pch_iobp_update(0xec000394, ~0, 0xf << 16); - pch_iobp_update(0xec000096, ~0x3ff, 1); - pch_iobp_update(0xec000196, ~0x3ff, 1); - pch_iobp_update(0xec000296, ~0x3ff, 1); - pch_iobp_update(0xec000396, ~0x3ff, 1); - pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); - pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); - pch_iobp_update(0xea00008d, ~0, 3 << 20); - pch_iobp_update(0xea00018d, ~0, 3 << 20); + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); + pch_iobp_update(0xec000084, ~(1 << 31), 0); + pch_iobp_update(0xec000184, ~(1 << 31), 0); + pch_iobp_update(0xec000284, ~(1 << 31), 0); + pch_iobp_update(0xec000384, ~(1 << 31), 0); + pch_iobp_update(0xec000094, ~0, 0xf << 16); + pch_iobp_update(0xec000194, ~0, 0xf << 16); + pch_iobp_update(0xec000294, ~0, 0xf << 16); + pch_iobp_update(0xec000394, ~0, 0xf << 16); + pch_iobp_update(0xec000096, ~0x3ff, 1); + pch_iobp_update(0xec000196, ~0x3ff, 1); + pch_iobp_update(0xec000296, ~0x3ff, 1); + pch_iobp_update(0xec000396, ~0x3ff, 1); + pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); + pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); + pch_iobp_update(0xea00008d, ~0, 3 << 20); + pch_iobp_update(0xea00018d, ~0, 3 << 20); + } /* TODO: Figure out what these writes mean */ pch_iobp_update(0xec0007b2, 0, 0x04514b5e); -- To view, visit https://review.coreboot.org/c/coreboot/+/49178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Gerrit-Change-Number: 49178 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49181 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ...................................................................... [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge Both ends of the DMI link must use the same TC/VC mapping. Since the register values are identical, pass the northbridge values as parameters and have the southbridge code use them. This prevents any inconsistency. Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 27 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49181/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index bcf3e4c..7d536b5 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -180,26 +180,33 @@ printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* - * Virtual Channel resources must match settings in RCBA! - * * Channel Vp and Vm are documented in: * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */ - /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0 */ + const u32 vc0 = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1 */ + const u32 vc1 = (1 << 31) | (1 << 24) | (0x11 << 1); + + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + const u32 vcp = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + const u32 vcm = (1 << 31) | (7 << 24) | (0x40 << 1); + + DMIBAR32(DMIVC0RCTL) = vc0; + DMIBAR32(DMIVC1RCTL) = vc1; + DMIBAR32(DMIVCPRCTL) = vcp; + DMIBAR32(DMIVCMRCTL) = vcm; /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1; - early_pch_init_native_dmi_post(); + /* Ensure the PCH side uses the same virtual channel settings */ + early_pch_init_native_dmi_post(vc0, vc1, vcp, vcm); /* * BIOS Requirement: Check if DMI VC Negotiation was successful. diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 251ff86..eac8e1f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -28,7 +28,7 @@ RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; } -void early_pch_init_native_dmi_post(void) +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) { u32 reg32; @@ -42,47 +42,21 @@ RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0; - /* - * Virtual Channel resources must match settings in DMIBAR! - * - * Some of the following settings are taken from - * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel - * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and - * serialice traces. - */ + /* Virtual Channel 0 */ + RCBA32(V0CTL) = vc0; - /* Virtual Channel 0 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC0 and TC3 and TC4 to VC0. - */ - - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - - /* Virtual Channel 1 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC1 and TC5 to VC1. - */ - RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Virtual Channel 1 */ + RCBA32(V1CTL) = vc1; /* Read back register */ RCBA32(V1CTL); - /* Virtual Channel private Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC2 and TC6 to VCp. - */ - RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Virtual Channel private */ + RCBA32(CIR31) = vcp; /* Read back register */ RCBA32(CIR31); - /* Virtual Channel ME Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC7 to VCm. - */ - RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* Virtual Channel ME */ + RCBA32(CIR32) = vcm; /* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 42c56a2..5eaaf51 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -63,7 +63,7 @@ void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -void early_pch_init_native_dmi_post(void); +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm); struct southbridge_usb_port { -- To view, visit https://review.coreboot.org/c/coreboot/+/49181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Gerrit-Change-Number: 49181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Split `pch_iobp_update` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49179 ) Change subject: sb/intel/bd82x6x: Split `pch_iobp_update` function ...................................................................... sb/intel/bd82x6x: Split `pch_iobp_update` function A follow-up needs to use the value of an IOBP register in a condition, so split the read and write operations into independent functions. Change-Id: Ic8fe5be8f0cf8e4672d3e32db7746609ff5da841 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/49179/1 diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 3fad12e..bd1b4cd 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -73,7 +73,7 @@ return 0; } -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +u32 pch_iobp_read(u32 address) { u32 data; @@ -85,24 +85,26 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) - return; + return 0; /* Read IOBP data */ data = RCBA32(IOBPD); if (!iobp_poll()) - return; + return 0; /* Check for successful transaction */ if ((RCBA32(IOBPS) & 0x6) != 0) { printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; + return 0; } - /* Update the data */ - data &= andvalue; - data |= orvalue; + return data; +} +void pch_iobp_write(u32 address, u32 data) +{ /* WRITE OPCODE */ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) RCBA32(IOBPS) = IOBPS_RW_BX; @@ -116,3 +118,14 @@ if (!iobp_poll()) return; } + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3b91e31..42c56a2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -43,6 +43,9 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); + +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8fe5be8f0cf8e4672d3e32db7746609ff5da841 Gerrit-Change-Number: 49179 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49180 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update ...................................................................... [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update This one IOBP register only needs to be updated if its bit 20 is zero. Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/49180/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e86297b..251ff86 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -181,8 +181,8 @@ pch_iobp_update(0xea0000a9, ~(0x3ff << 3), 0x29f << 3); pch_iobp_update(SATA_IOBP_SP1G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); - /* TODO: Needs special handling */ - pch_iobp_update(0xea007f05, 0, 0x00010642); + if ((pch_iobp_read(0xea007f05) & 1 << 20) == 0) + pch_iobp_update(0xea007f05, ~(7 << 8), 6 << 8); pch_iobp_update(0xea0040b7, ~0xffff, 0xc91c); pch_iobp_update(0xea0040b8, ~0xffff, 0xc91c); -- To view, visit https://review.coreboot.org/c/coreboot/+/49180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Gerrit-Change-Number: 49180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Fix replay issues
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49165 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Fix replay issues ...................................................................... [UNTESTED] sb/intel/bd82x6x: Fix replay issues Rewrite suspicious register handling as per reference code. Proper handling of the value in the RPC register needs some IOBP operations, and will be done in a follow-up once `pch_iobp_update` can be used. Change-Id: I40c7eb2323c22185ca8184166b3ca225c61e9299 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/49165/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 767d3ad..6daafe0 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -16,8 +16,6 @@ #include "pch.h" #include "chip.h" -#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) - static void wait_iobp(void) { while (RCBA8(IOBPS) & 1) @@ -67,13 +65,17 @@ void early_pch_init_native_dmi_post(void) { - RCBA32(CIR0); // !!! = 0x01200654 - RCBA32(CIR0) = 0x01200654; - RCBA32(CIR0); // !!! = 0x01200654 - RCBA32(CIR0) = 0x012a0654; - RCBA32(CIR0); // !!! = 0x012a0654 - RCBA8(UPDCR); // !!! = 0x00 - RCBA8(UPDCR) = 0x05; + u32 reg32; + + reg32 = RCBA32(CIR0); + reg32 &= ~(0xff << 16 | 0xfff); + reg32 |= 0x654; /* Set the recommended TC encoding */ + reg32 |= 0x20 << 16; + reg32 |= 0x0a << 16; /* VCp enabled */ + RCBA32(CIR0) = reg32; + RCBA32(CIR0); /* Read back for posted write to take effect */ + + RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0; /* * Virtual Channel resources must match settings in DMIBAR! @@ -135,23 +137,21 @@ void early_pch_init_native(void) { - pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); + /* Lock down PMBASE */ + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, 1 << 1); - RCBA32(CIR1) = 0x00109000; - RCBA32(REC); // !!! = 0x00000000 - RCBA32(REC) = 0x40000000; + RCBA32(CIR1) = 0x00109000; /* Mask some errors */ + RCBA32_OR(REC, 1 << 30); RCBA32(0x100c) = 0x01110000; - RCBA8(0x2340) = 0x1b; - RCBA32(CIR6); // !!! = 0x0a080000 - RCBA32(CIR6) = 0x0a280000; - RCBA32(0x2310); // !!! = 0xc809605b - RCBA32(0x2310) = 0xa809605b; + RCBA8(0x2340) = 0x1b; /* Set Gen 1 Common Clock N_FTS */ + RCBA32_OR(CIR6, 1 << 21); + RCBA32_AND_OR(0x2310, ~(3 << 29), 1 << 29); RCBA32(DMC2) = 0x00854c74; - RCBA8(RPC); // !!! = 0x00 - RCBA32(0x2310); // !!! = 0xa809605b - RCBA32(0x2310) = 0xa809605b; - RCBA32(0x2310); // !!! = 0xa809605b - RCBA32(0x2310) = 0xa809605b; + + /* TODO: Handle non-zero cases */ + RCBA8(RPC); + RCBA32_AND_OR(0x2310, ~(3 << 22), 0); + RCBA32_AND_OR(0x2310, ~(3 << 20), 0); write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133); -- To view, visit https://review.coreboot.org/c/coreboot/+/49165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c7eb2323c22185ca8184166b3ca225c61e9299 Gerrit-Change-Number: 49165 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: [WIP] Make UartSub driver bind to LPSS UART
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70156?usp=email ) Change subject: [WIP] Make UartSub driver bind to LPSS UART ...................................................................... Abandoned No interest in pursuing this -- To view, visit https://review.coreboot.org/c/coreboot/+/70156?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I197ff2df2e4506994daa1ae72026b17ff662a9ab Gerrit-Change-Number: 70156 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Patrick Rudolph, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/c/coreboot/+/79784/comment/82f25397_eb223d41 : PS3, Line 784: if ((IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) || : IS_SANDY_CPU(ctrl->cpu)) I believe the tCK check is to improve stability at high clock speeds. Sandy Bridge needs to be overclocked quite a bit to run at 1066 MHz (DDR3-2133), and it's likely it would benefit from SRT being disabled. So, we could simplify this check to `ctrl->tCK >= TCK_1066MHZ`. -- To view, visit https://review.coreboot.org/c/coreboot/+/79784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Gerrit-Change-Number: 79784 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 11 Apr 2024 17:41:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79783?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis ...................................................................... Patch Set 3: (2 comments) File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/c/coreboot/+/79783/comment/b77d3cad_981550f8 : PS3, Line 781: rank/2 nit: spacing around `/` Also, for readability, an auxiliary constant would help: ```c const int slot = rank / 2; ``` https://review.coreboot.org/c/coreboot/+/79783/comment/f06e4676_d9a48b18 : PS3, Line 799: reg32 &= 1 << (rank / 2 + 14) | 1 << (rank / 2 + 6); I don't think this should be changed. The code reads the MR2 shadow register, keeps the values of the other slot's bits, combines this with the MR2 contents, then adds the slot-specific bits, and finally writes back the updated value. Right now, this would result in the bits for the first rank being cleared, which is bad (test with a DIMM that uses address mirroring on the first slot, and any other DIMM in the second slot of the same channel) -- To view, visit https://review.coreboot.org/c/coreboot/+/79783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55 Gerrit-Change-Number: 79783 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 17:36:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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