Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81888?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/packardbell/ms2290: Correct header included
......................................................................
mb/packardbell/ms2290: Correct header included
It uses ibexpeak southbridge and should include its pch.h,
not bd82x6x's.
TEST=Timeless binary did not change.
Change-Id: Iafa83b7f3c1cd2d8ab9af51aa331ca673d9a66df
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81888
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/packardbell/ms2290/mainboard.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Angel Pons: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c
index 855bbb3..07297aa 100644
--- a/src/mainboard/packardbell/ms2290/mainboard.c
+++ b/src/mainboard/packardbell/ms2290/mainboard.c
@@ -2,7 +2,7 @@
#include <device/device.h>
#include <northbridge/intel/ironlake/ironlake.h>
-#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/ibexpeak/pch.h>
#include <ec/acpi/ec.h>
#include <drivers/intel/gma/int15.h>
#include <pc80/keyboard.h>
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Change subject: soc/sifive/fu540/chip.c: Add RAM resources
......................................................................
Patch Set 1:
(1 comment)
File src/soc/sifive/fu540/chip.c:
https://review.coreboot.org/c/coreboot/+/81909/comment/91b99c5a_0a016481 :
PS1, Line 15: .enable_dev
Having this on a read_resource device ops is more appropriate.
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Change subject: mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81910/comment/71f0c383_92087751 :
PS1, Line 18: The coreboot LZ4 decompression code does some misaligned access during
: decompression
> I don't know how deep this rabbit hole goes, but wouldn't it be
> better to fix the code? AIUI, unaligned accesses are less efficient
> but decompression should be most performant?
Best of both worlds: use bootblock with decompressor stage without a separate romstage? Still it might be desirable to have a separate romstage in the VBOOT use case?
About the misaligned access: is -mstrict-align passed to the compiler?
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Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81554?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: device/device_util: Rename dev_get_pci_domain
......................................................................
device/device_util: Rename dev_get_pci_domain
In coreboot, domain indicates hardware units that provide/group
resource windows, For Xeon-SP, domains are PCIe compatible and
further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX.
Rename dev_get_pci_domain to dev_get_domain to align with coreboot
concept and distinguish from Xeon-SP concept.
TEST=Build and boot on intel/archercity CRB
Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/device/device_util.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/81554/9
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Shuo Liu has uploaded a new patch set (#21) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: device/device_util: Use const qualifier
......................................................................
device/device_util: Use const qualifier
Allows to use the function in more places that expect the
struct device to be readonly.
TEST=Build and boot on intel/archercity CRB
Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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---
M src/device/device_util.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 21 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/21
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Change subject: device/device_util: Use const qualifier
......................................................................
Patch Set 20:
(2 comments)
File src/device/device_util.c:
https://review.coreboot.org/c/coreboot/+/81275/comment/e358bb05_fb7fb959 :
PS20, Line 3: #include <assert.h>
> Not needed anymore, I guess.
Done
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/81275/comment/0690189d_f7a78eca :
PS20, Line 139: if (dev->path.type == DEVICE_PATH_DOMAIN)
: domain = dev;
: else
: domain = dev_get_pci_domain(dev);
> Just for the future: this pattern wouldn't be necessary if dev_get_domain() […]
I suppose this is still needed, since dev_get_domain() cannot handle the case where the input struct device *dev is a domain originally. Or we further upgrade dev_get_domain() to handle the case above, which needs a separate patch.
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Change subject: mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81910/comment/3a6507ef_d355e622 :
PS1, Line 18: The coreboot LZ4 decompression code does some misaligned access during
: decompression
I don't know how deep this rabbit hole goes, but wouldn't it be
better to fix the code? AIUI, unaligned accesses are less efficient
but decompression should be most performant?
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Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File Documentation/mainboard/hp/pro_3500_series_flash.jpg:
PS2:
> Seems ok to me. Even if there'll be somebody who has trouble viewing it, that's […]
Done
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Change subject: arch/x86: Prevent .text/.init overlap with older linkers
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/81886/comment/6679e933_932dbc9a :
PS2, Line 415: PROGRAM_SZ_EXTRA_SPACE
maybe a bit more specific: X86_BOOTBLOCK_EXTRA_PROGRAM_SZ ?
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