Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81946?usp=email )
Change subject: nb/intel/gm45: Call `mb_post_raminit_setup()` later
......................................................................
nb/intel/gm45: Call `mb_post_raminit_setup()` later
The only implementations of `mb_post_raminit_setup()` in the tree are
found in Lenovo ThinkPads. These boards use this function to toggle a
SMBus mux, which makes the DIMM SPDs inaccessible. Given that the SPD
data is needed in `setup_sdram_meminfo()` and that there are no other
side-effects, simply move the call to `mb_post_raminit_setup()` after
the call to `setup_sdram_meminfo()`.
TEST=Verify SMBIOS Type 17 information for lenovo/x200 is correct.
Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/gm45/romstage.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/81946/1
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 9ed3c00..bc17618 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -74,8 +74,6 @@
raminit(&sysinfo, s3resume);
- mb_post_raminit_setup();
-
/* Disable D4F0 (unknown signal controller). */
pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000);
@@ -93,6 +91,8 @@
setup_sdram_meminfo(&sysinfo);
+ mb_post_raminit_setup();
+
romstage_handoff_init(cbmem_initted && s3resume);
printk(BIOS_SPEW, "exit main()\n");
--
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Gerrit-Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Gerrit-Change-Number: 81946
Gerrit-PatchSet: 1
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81930?usp=email
to look at the new patch set (#2).
Change subject: sb/intel/ibexpeak: Drop USB3 settings from devicetree
......................................................................
sb/intel/ibexpeak: Drop USB3 settings from devicetree
ibexpeak has no USB 3 capabilities.
They were kept briefly when its devicetree structure was split from
bd82x6x in commit ab4de83f4330 ("sb/intel/ibexpeak: Sever bd82x6x
source dependency") to verify correctness. With that done, they
can go.
Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/southbridge/intel/ibexpeak/chip.h
1 file changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/81930/2
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81930?usp=email )
Change subject: sb/intel/ibexpeak: Drop USB3 settings from devicetree
......................................................................
Patch Set 1: Code-Review+2
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Jean Lucas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81861?usp=email )
Change subject: nb/intel/gm45: Fill in memory info
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
Tested on X200 with dual-rank DIMMs.
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