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Change subject: haswell NRI: Initialise MPLL
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File src/northbridge/intel/haswell/native_raminit/init_mpll.c:
https://review.coreboot.org/c/coreboot/+/64184/comment/672cb062_0889687f :
PS5, Line 209: wait_for_first_rcomp
can this be a separate step in cold_boot[] ?
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Change subject: payloads/external: Call $(strip_quotes ) on prebuilt iPXE path
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Patch Set 1: Code-Review+1
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Change subject: acpigen_ps2_keybd: Add Fn key to linux,keymap
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Patch Set 3:
(2 comments)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/81895/comment/6517873f_9571f320 :
PS2, Line 19: default 0
> Why this default?
The default is 0 since, in my experience, most keyboards don't generate a scancode when Fn is pressed. A value of 0 is ignored, therefore no action is taken for those keyboards.
https://review.coreboot.org/c/coreboot/+/81895/comment/fbf56285_a2784747 :
PS2, Line 22: Fn key is pressed.
> Mention that 0 is ignored?
Done
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I'd like you to reexamine a change. Please visit
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Code-Review+2 by Shelley Chen, Verified+1 by build bot (Jenkins)
Change subject: acpigen_ps2_keybd: Add Fn key to linux,keymap
......................................................................
acpigen_ps2_keybd: Add Fn key to linux,keymap
Some devices may generate scancodes for the Fn key if they have one.
If they do, we should add them to the linux,keymap binding.
BUG=b:333096023
TEST=Flash DUT that emits a scancode for the Fn key, verify that it is
mapped to KEY_FN in the Linux kernel using `evtest` when pressing the Fn
key.
Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c
Signed-off-by: Aseda Aboagye <aaboagye(a)google.com>
---
M src/acpi/Kconfig
M src/acpi/acpigen_ps2_keybd.c
2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81895/3
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Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
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Patch Set 7:
(1 comment)
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/1bfa989b_b7d15241 :
PS7, Line 125: device ref pch_espi on
What about `gen1_dec` to access I/O Range for ITE SuperIO HWM/EC?
[1] https://github.com/coreboot/coreboot/blob/main/src/soc/intel/tigerlake/espi…
[2] https://github.com/coreboot/coreboot/blob/main/src/mainboard/intel/tglrvp/v…
[3] https://github.com/coreboot/coreboot/blob/main/src/mainboard/asrock/h110m/d…
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
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Patch Set 1: Code-Review+1
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Change subject: mb/google/brya: Enable UFS driver for edk2 payload
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Patch Set 2: Code-Review+1
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