coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: lint/checkpatch: Reduce the difference with linux v6.8
by Elyes Haouas (Code Review) 17 Apr '24

17 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81951?usp=email ) Change subject: lint/checkpatch: Reduce the difference with linux v6.8 ...................................................................... lint/checkpatch: Reduce the difference with linux v6.8 Change-Id: I4898c4b11c791a5bd3895db656e03d7d5c46e933 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/81951/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 5afdc4e..79e345f 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -2920,7 +2920,7 @@ # A Fixes: or Link: line or signature tag line $commit_log_possible_stack_dump)) { WARN("COMMIT_LOG_LONG_LINE", - "Possible unwrapped commit description (prefer a maximum 72 chars per line)\n" . $herecurr); + "Prefer a maximum 72 chars per line (possible unwrapped commit description?)\n" . $herecurr); $commit_log_long_line = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4898c4b11c791a5bd3895db656e03d7d5c46e933 Gerrit-Change-Number: 81951 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lint/checkpatch: Do not require an empty line before error injection
by Elyes Haouas (Code Review) 17 Apr '24

17 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81950?usp=email ) Change subject: lint/checkpatch: Do not require an empty line before error injection ...................................................................... lint/checkpatch: Do not require an empty line before error injection This updates the script to upsteam version 6.8 https://github.com/torvalds/linux/commit/2f9dadba5ba02e1510a04ce57ebfb9e08f… Change-Id: I40708185df4036f7aaa1dcb419663c9e54aad44a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/81950/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 16b6bd3..5afdc4e 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -3565,7 +3565,7 @@ if ($prevline =~ /^[\+ ]};?\s*$/ && $line =~ /^\+/ && !($line =~ /^\+\s*$/ || - $line =~ /^\+\s*EXPORT_SYMBOL/ || + $line =~ /^\+\s*(?:EXPORT_SYMBOL|early_param|ALLOW_ERROR_INJECTION)/ || $line =~ /^\+\s*MODULE_/i || $line =~ /^\+\s*\#\s*(?:end|elif|else)/ || $line =~ /^\+[a-z_]*init/ || -- To view, visit https://review.coreboot.org/c/coreboot/+/81950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40708185df4036f7aaa1dcb419663c9e54aad44a Gerrit-Change-Number: 81950 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lint/checkpatch: Add __aligned to the list of attribute notes
by Elyes Haouas (Code Review) 17 Apr '24

17 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81949?usp=email ) Change subject: lint/checkpatch: Add __aligned to the list of attribute notes ...................................................................... lint/checkpatch: Add __aligned to the list of attribute notes This updates the script to upsteam version 6.8 https://github.com/torvalds/linux/commit/2f9dadba5ba02e1510a04ce57ebfb9e08f… Change-Id: I9274e8b5ed5ada27c290c462b0c59eccf1b0b60d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/checkpatch.pl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/81949/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index b6ac890..16b6bd3 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -517,6 +517,7 @@ __ro_after_init| __kprobes| $InitAttribute| + __aligned\s*$.*$| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| -- To view, visit https://review.coreboot.org/c/coreboot/+/81949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9274e8b5ed5ada27c290c462b0c59eccf1b0b60d Gerrit-Change-Number: 81949 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: payloads/external: Call $(strip_quotes ) on prebuilt iPXE path
by Maximilian Brune (Code Review) 17 Apr '24

17 Apr '24

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81947?usp=email ) Change subject: payloads/external: Call $(strip_quotes ) on prebuilt iPXE path ...................................................................... payloads/external: Call $(strip_quotes ) on prebuilt iPXE path Currently, we keep the double-quotes from Kconfig, resulting in an invalid path. So just call `strip_quotes` like we do with all other paths from Kconfig. Change-Id: Ibcaa59be0fdd84d1fb9e061394fd9b0f7aa1830b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81947 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 9b79f1a..5d385a4 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -344,7 +344,7 @@ PXE_ROM_PCI_ID:=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) ifeq ($(CONFIG_PXE_ROM),y) -PXE_ROM_FILE:=$(CONFIG_PXE_ROM_FILE) +PXE_ROM_FILE:=$(call strip_quotes,$(CONFIG_PXE_ROM_FILE)) endif ifeq ($(CONFIG_BUILD_IPXE),y) PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom -- To view, visit https://review.coreboot.org/c/coreboot/+/81947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcaa59be0fdd84d1fb9e061394fd9b0f7aa1830b Gerrit-Change-Number: 81947 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: ec/google/chromeec: Update EC headers
by Felix Held (Code Review) 17 Apr '24

17 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81932?usp=email ) Change subject: ec/google/chromeec: Update EC headers ...................................................................... ec/google/chromeec: Update EC headers Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81932 Reviewed-by: Forest Mittelberg <bmbm(a)google.com> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 154 insertions(+), 79 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved Forest Mittelberg: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h index 2b0bdde..453f507 100644 --- a/src/ec/google/chromeec/ec_cmd_api.h +++ b/src/ec/google/chromeec/ec_cmd_api.h @@ -107,6 +107,20 @@ NULL, 0); } +static inline int ec_cmd_fp_frame(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_frame *p, + uint8_t *r) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_FRAME, 0, p, sizeof(*p), r, + p->size); +} + +static inline int ec_cmd_fp_template(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_template *p, + int size) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_TEMPLATE, 0, p, size, NULL, 0); +} /* * Section 2: EC interface functions that can be generated with the help * of template macros. @@ -280,9 +294,13 @@ flash_region_info, flash_region_info); _CROS_EC_C0_F_RF(EC_CMD_FLASH_SPI_INFO, flash_spi_info); _CROS_EC_C0_F_PF(EC_CMD_FORCE_LID_OPEN, force_lid_open); -_CROS_EC_C0_F_PF_RF(EC_CMD_FP_MODE, fp_mode); _CROS_EC_C0_F_PF(EC_CMD_FP_SEED, fp_seed); +_CROS_EC_C0_F_PF_RF(EC_CMD_FP_MODE, fp_mode); +_CROS_EC_C0_F_PF_RF(EC_CMD_FP_READ_MATCH_SECRET, fp_read_match_secret); +_CROS_EC_C0_F_RF(EC_CMD_FP_ENC_STATUS, fp_encryption_status); _CROS_EC_C0_F_RF(EC_CMD_FP_STATS, fp_stats); +_CROS_EC_C1_F_PF(EC_CMD_FP_CONTEXT, fp_context); +_CROS_EC_CV_F_R(EC_CMD_FP_INFO, 1, fp_info, fp_info); _CROS_EC_CV_F_R(EC_CMD_GET_BOARD_VERSION, 0, get_board_version, board_version); _CROS_EC_C0_F_RF(EC_CMD_GET_BOOT_TIME, get_boot_time); _CROS_EC_C0_F_RF(EC_CMD_GET_CHIP_INFO, get_chip_info); @@ -292,8 +310,9 @@ _CROS_EC_C0_F_RF(EC_CMD_GET_COMMS_STATUS, get_comms_status); _CROS_EC_C0_F_RF(EC_CMD_GET_FEATURES, get_features); _CROS_EC_CV_F_R(EC_CMD_GET_KEYBD_CONFIG, 0, get_keybd_config, keybd_config); -_CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event); _CROS_EC_C0_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); +_CROS_EC_C1_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); +_CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event_v1); _CROS_EC_C0_F_PF_RF(EC_CMD_GET_PD_PORT_CAPS, get_pd_port_caps); _CROS_EC_C0_F_RF(EC_CMD_GET_PROTOCOL_INFO, get_protocol_info); _CROS_EC_CV_F_R(EC_CMD_GET_UPTIME_INFO, 0, get_uptime_info, uptime_info); @@ -304,7 +323,7 @@ _CROS_EC_C0_F_PF(EC_CMD_GPIO_SET, gpio_set); _CROS_EC_CV_F_P_R(EC_CMD_GSV_PAUSE_IN_S5, 0, gsv_pause_in_s5, get_set_value, get_set_value); -_CROS_EC_C0_F_PF(EC_CMD_HANG_DETECT, hang_detect); +_CROS_EC_C0_F_PF_RF(EC_CMD_HANG_DETECT, hang_detect); _CROS_EC_C0_F_PF_RF(EC_CMD_HELLO, hello); _CROS_EC_C0_F_PF_RF(EC_CMD_HIBERNATION_DELAY, hibernation_delay); _CROS_EC_C0_F_PF_RF(EC_CMD_HOST_EVENT, host_event); diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index b66f9d3..0d474cb 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -522,9 +522,9 @@ #define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ -#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f) +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) #define EC_ACPI_MEM_USB_RETIMER_OP(x) \ - (((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data @@ -690,6 +690,8 @@ EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + EC_RES_COUNT, + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); @@ -737,6 +739,39 @@ #endif +/* clang-format off */ +#define EC_STATUS_TEXT \ + { \ + EC_MAP_ITEM(EC_RES_SUCCESS, SUCCESS), \ + EC_MAP_ITEM(EC_RES_INVALID_COMMAND, INVALID_COMMAND), \ + EC_MAP_ITEM(EC_RES_ERROR, ERROR), \ + EC_MAP_ITEM(EC_RES_INVALID_PARAM, INVALID_PARAM), \ + EC_MAP_ITEM(EC_RES_ACCESS_DENIED, ACCESS_DENIED), \ + EC_MAP_ITEM(EC_RES_INVALID_RESPONSE, INVALID_RESPONSE), \ + EC_MAP_ITEM(EC_RES_INVALID_VERSION, INVALID_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_CHECKSUM, INVALID_CHECKSUM), \ + EC_MAP_ITEM(EC_RES_IN_PROGRESS, IN_PROGRESS), \ + EC_MAP_ITEM(EC_RES_UNAVAILABLE, UNAVAILABLE), \ + EC_MAP_ITEM(EC_RES_TIMEOUT, TIMEOUT), \ + EC_MAP_ITEM(EC_RES_OVERFLOW, OVERFLOW), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER, INVALID_HEADER), \ + EC_MAP_ITEM(EC_RES_REQUEST_TRUNCATED, REQUEST_TRUNCATED), \ + EC_MAP_ITEM(EC_RES_RESPONSE_TOO_BIG, RESPONSE_TOO_BIG), \ + EC_MAP_ITEM(EC_RES_BUS_ERROR, BUS_ERROR), \ + EC_MAP_ITEM(EC_RES_BUSY, BUSY), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_VERSION, INVALID_HEADER_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_CRC, INVALID_HEADER_CRC), \ + EC_MAP_ITEM(EC_RES_INVALID_DATA_CRC, INVALID_DATA_CRC), \ + EC_MAP_ITEM(EC_RES_DUP_UNAVAILABLE, DUP_UNAVAILABLE), \ + } +/* clang-format on */ + +#ifndef __cplusplus +#define EC_MAP_ITEM(k, v) [k] = #v +BUILD_ASSERT(ARRAY_SIZE(((const char *[])EC_STATUS_TEXT)) == EC_RES_COUNT); +#undef EC_MAP_ITEM +#endif + /* * Host event codes. ACPI query EC command uses code 0 to mean "no event * pending". We explicitly specify each value in the enum listing so they won't @@ -1658,6 +1693,10 @@ * The EC supports DP2.1 capability */ EC_FEATURE_TYPEC_DP2_1 = 52, + /* + * The MCU is System Companion Processor Core 1 + */ + EC_FEATURE_SCP_C1 = 53, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2864,6 +2903,7 @@ MOTIONSENSE_CHIP_BMI323 = 28, MOTIONSENSE_CHIP_BMI220 = 29, MOTIONSENSE_CHIP_CM32183 = 30, + MOTIONSENSE_CHIP_VEML3328 = 31, MOTIONSENSE_CHIP_MAX, }; @@ -4096,15 +4136,15 @@ } __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ -#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF) -#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F) +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 #define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ - (((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) + (((fpe) & 0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) #define EC_MKBP_FP_MATCH_IDX_OFFSET 12 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 #define EC_MKBP_FP_MATCH_IDX(fpe) \ - (((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) + (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) #define EC_MKBP_FP_ENROLL BIT(27) #define EC_MKBP_FP_MATCH BIT(28) #define EC_MKBP_FP_FINGER_DOWN BIT(29) @@ -4122,6 +4162,7 @@ #define EC_MKBP_FP_ERR_MATCH_NO 0 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 #define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_AUTH_FAIL 8 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 #define EC_MKBP_FP_ERR_MATCH_YES 1 @@ -4707,60 +4748,50 @@ } __ec_align1; /*****************************************************************************/ -/* Power button hang detect */ - +/* AP hang detect */ #define EC_CMD_HANG_DETECT 0x009F -/* Reasons to start hang detection timer */ -/* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS BIT(0) +#define EC_HANG_DETECT_MIN_TIMEOUT 5 -/* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE BIT(1) +/* EC hang detect commands */ +enum ec_hang_detect_cmds { + /* Reload AP hang detect timer. */ + EC_HANG_DETECT_CMD_RELOAD = 0x0, -/* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN BIT(2) + /* Stop AP hang detect timer. */ + EC_HANG_DETECT_CMD_CANCEL = 0x1, -/* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME BIT(3) + /* Configure watchdog with given reboot timeout and + * cancel currently running AP hand detect timer. + */ + EC_HANG_DETECT_CMD_SET_TIMEOUT = 0x2, -/* Reasons to cancel hang detection */ + /* Get last hang status - whether the AP boot was clear or not */ + EC_HANG_DETECT_CMD_GET_STATUS = 0x3, -/* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) - -/* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) - -/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND BIT(10) - -/* - * If this flag is set, all the other fields are ignored, and the hang detect - * timer is started. This provides the AP a way to start the hang timer - * without reconfiguring any of the other hang detect settings. Note that - * you must previously have configured the timeouts. - */ -#define EC_HANG_START_NOW BIT(30) - -/* - * If this flag is set, all the other fields are ignored (including - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer - * without reconfiguring any of the other hang detect settings. - */ -#define EC_HANG_STOP_NOW BIT(31) + /* Clear last hang status. Called when AP is rebooting/shutting down + * gracefully. + */ + EC_HANG_DETECT_CMD_CLEAR_STATUS = 0x4 +}; struct ec_params_hang_detect { - /* Flags; see EC_HANG_* */ - uint32_t flags; + uint16_t command; /* enum ec_hang_detect_cmds */ + /* Timeout in seconds before generating reboot */ + uint16_t reboot_timeout_sec; +} __ec_align2; - /* Timeout in msec before generating host event, if enabled */ - uint16_t host_event_timeout_msec; - - /* Timeout in msec before generating warm reboot, if enabled */ - uint16_t warm_reboot_timeout_msec; -} __ec_align4; - +/* Status codes that describe whether AP has boot normally or the hang has been + * detected and EC has reset AP + */ +enum ec_hang_detect_status { + EC_HANG_DETECT_AP_BOOT_NORMAL = 0x0, + EC_HANG_DETECT_AP_BOOT_EC_WDT = 0x1, + EC_HANG_DETECT_AP_BOOT_COUNT, +}; +struct ec_response_hang_detect { + uint8_t status; /* enum ec_hang_detect_status */ +} __ec_align1; /*****************************************************************************/ /* Commands for battery charging */ @@ -4817,7 +4848,7 @@ CS_PARAM_DEBUG_MANUAL_MODE, CS_PARAM_DEBUG_SEEMS_DEAD, CS_PARAM_DEBUG_SEEMS_DISCONNECTED, - CS_PARAM_DEBUG_BATT_REMOVED, + CS_PARAM_DEBUG_BATT_REMOVED, /* Deprecated */ CS_PARAM_DEBUG_MANUAL_CURRENT, CS_PARAM_DEBUG_MANUAL_VOLTAGE, CS_PARAM_DEBUG_MAX = 0x2ffff, @@ -5193,8 +5224,8 @@ * bits[31:28]: port number */ #define EC_MKBP_EVENT_CEC_PACK(events, port) \ - (((events)&GENMASK(27, 0)) | (((port)&0xf) << 28)) -#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event)&GENMASK(27, 0)) + (((events) & GENMASK(27, 0)) | (((port) & 0xf) << 28)) +#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event) & GENMASK(27, 0)) #define EC_MKBP_EVENT_CEC_GET_PORT(event) (((event) >> 28) & 0xf) /* CEC message from the AP to be written on the CEC bus */ @@ -6064,9 +6095,9 @@ #define PD_LOG_PORT_MASK 0xe0 #define PD_LOG_PORT_SHIFT 5 #define PD_LOG_PORT_SIZE(port, size) \ - (((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK)) + (((port) << PD_LOG_PORT_SHIFT) | ((size) & PD_LOG_SIZE_MASK)) #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) /* PD event log : entry types */ /* PD MCU events */ @@ -6316,6 +6347,7 @@ /* struct board_batt_params */ CBI_TAG_BATTERY_CONFIG = 12, /* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */ + CBI_TAG_BATTERY_CONFIG_15 = 27, /* Last entry */ CBI_TAG_COUNT, @@ -6323,7 +6355,7 @@ union ec_common_control { struct { - uint32_t bcic_enabled : 1; + uint32_t bcic_enabled : 1; /* Unused. Take it over as yours. */ }; uint32_t raw_value; }; @@ -6565,6 +6597,7 @@ enum ec_chip_type { EC_CHIP_TYPE_CBI_EEPROM = 0, EC_CHIP_TYPE_TCPC = 1, + EC_CHIP_TYPE_PDC = 2, EC_CHIP_TYPE_COUNT, EC_CHIP_TYPE_MAX = 0xFF, }; @@ -6760,6 +6793,9 @@ TK_KBD_BKLIGHT_TOGGLE = 18, TK_MICMUTE = 19, TK_MENU = 20, + TK_DICTATE = 21, + + TK_COUNT }; /* @@ -6784,6 +6820,11 @@ */ #define KEYBD_CAP_SCRNLOCK_KEY BIT(2) +/* + * Whether the keyboard has an assistant key. + */ +#define KEYBD_CAP_ASSISTANT_KEY BIT(3) + struct ec_response_keybd_config { /* * Number of top row keys, excluding Esc and Screenlock. @@ -7123,6 +7164,7 @@ #define PD_STATUS_EVENT_VDM_REQ_REPLY BIT(6) #define PD_STATUS_EVENT_VDM_REQ_FAILED BIT(7) #define PD_STATUS_EVENT_VDM_ATTENTION BIT(8) +#define PD_STATUS_EVENT_COUNT 9 /* * Encode and decode for BCD revision response @@ -7428,7 +7470,8 @@ #define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) #define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) /* Utility macro for extracting event bits. */ -#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) +#define EC_MKBP_PCHG_EVENT_MASK(e) \ + ((e) & GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) #define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) #define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) @@ -7726,7 +7769,7 @@ uint8_t reserved; } __packed __aligned(2); -/** +/* * The 'config' of a battery. */ struct board_batt_params { @@ -7734,9 +7777,22 @@ struct battery_info batt_info; } __packed __aligned(4); -#define SBS_MAX_STRING_SIZE 32 +/* + * The SBS defines a string object as a block of chars, 32 byte maximum, where + * the first byte indicates the number of chars in the block (excluding the + * first byte). + * + * Thus, the actual string length (i.e. the value strlen returns) is limited to + * 31 (=SBS_MAX_STR_SIZE). + * + * SBS_MAX_STR_OBJ_SIZE can be used as the size of a buffer for an SBS string + * object but also as a buffer for a c-lang string because the null terminating + * char also takes one byte. + */ +#define SBS_MAX_STR_SIZE 31 +#define SBS_MAX_STR_OBJ_SIZE (SBS_MAX_STR_SIZE + 1) -/** +/* * Header describing a battery config stored in CBI. Only struct_version has * size and position independent of struct_version. The rest varies as * struct_version changes. @@ -7776,8 +7832,8 @@ /* manuf_name, device_name, board_batt_params follow after this. */ } __packed; -#define BATT_CONF_MAX_SIZE \ - (sizeof(struct batt_conf_header) + SBS_MAX_STRING_SIZE * 2 + \ +#define BATT_CONF_MAX_SIZE \ + (sizeof(struct batt_conf_header) + SBS_MAX_STR_OBJ_SIZE * 2 + \ sizeof(struct board_batt_params)) /* @@ -7884,7 +7940,7 @@ }; /* Extracts the capture type from the sensor 'mode' word */ #define FP_CAPTURE_TYPE(mode) \ - (((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) + (((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ @@ -7898,7 +7954,7 @@ #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF) +#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) /* Unknown number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ @@ -8067,6 +8123,10 @@ #define FP_CONTEXT_STATUS_MATCH_PROCESSED_SET BIT(2) /* FP auth_nonce had been set or not*/ #define FP_CONTEXT_AUTH_NONCE_SET BIT(3) +/* FP user_id had been set or not*/ +#define FP_CONTEXT_USER_ID_SET BIT(4) +/* FP templates are unlocked for nonce context or not */ +#define FP_CONTEXT_TEMPLATE_UNLOCKED_SET BIT(5) struct ec_response_fp_encryption_status { /* Used bits in encryption engine status */ @@ -8184,15 +8244,11 @@ uint8_t enc_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; } __ec_align4; -/* Preload encrypted template into the MCU buffer */ -#define EC_CMD_FP_PRELOAD_TEMPLATE 0x0416 +/* Unlock the fpsensor template with the current nonce context */ +#define EC_CMD_FP_UNLOCK_TEMPLATE 0x0417 -struct ec_params_fp_preload_template { - uint32_t offset; - uint32_t size; - uint16_t fgr; - uint8_t reserved[2]; - uint8_t data[]; +struct ec_params_fp_unlock_template { + uint16_t fgr_num; } __ec_align4; /*****************************************************************************/ @@ -8303,10 +8359,10 @@ uint16_t design_capacity; uint16_t design_voltage; uint32_t cycle_count; - char manufacturer[32]; - char device_name[32]; - char serial[32]; - char chemistry[32]; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; } __ec_align4; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 4 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/x86: Update X86_64 memcpy for 4 byte copy
by Ashish Kumar Mishra (Code Review) 17 Apr '24

17 Apr '24

Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81959?usp=email ) Change subject: arch/x86: Update X86_64 memcpy for 4 byte copy ...................................................................... arch/x86: Update X86_64 memcpy for 4 byte copy The current 8 byte copy cannot write to spi flash, due to 4 byte limit. This affected MRC Cache R/W in X86_64. Hence update to 4 byte copy. BUG=None TEST=Build and boot google/rex 64-bit and verified MRC cache working. Change-Id: I1110cc18f5aa59c864e3cc04b9e6b3501ec4d54d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/arch/x86/memcpy.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81959/1 diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 9da2a75..9f6f1af 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -16,11 +16,11 @@ #if ENV_X86_64 asm volatile( - "rep ; movsq\n\t" - "mov %4,%%rcx\n\t" + "rep ; movsd\n\t" + "mov %4, %%rcx\n\t" "rep ; movsb\n\t" : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) + : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) : "memory" ); #else -- To view, visit https://review.coreboot.org/c/coreboot/+/81959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1110cc18f5aa59c864e3cc04b9e6b3501ec4d54d Gerrit-Change-Number: 81959 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/corsola: Add new board variant Veluza
by Felix Held (Code Review) 17 Apr '24

17 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81791?usp=email ) Change subject: mb/google/corsola: Add new board variant Veluza ...................................................................... mb/google/corsola: Add new board variant Veluza Add a new Krabby follower device 'Veluza'. BUG=b:333630131 BRANCH=corsola TEST=none Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 8 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 960d8f9..402f4cc 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -17,7 +17,8 @@ BOARD_GOOGLE_KRABBY || \ BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_SKITTY || \ - BOARD_GOOGLE_TENTACRUEL + BOARD_GOOGLE_TENTACRUEL || \ + BOARD_GOOGLE_VELUZA config BOARD_GOOGLE_STARYU_COMMON def_bool BOARD_GOOGLE_STARMIE || \ @@ -61,7 +62,8 @@ BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_SKITTY || \ BOARD_GOOGLE_STEELIX || \ - BOARD_GOOGLE_TENTACRUEL + BOARD_GOOGLE_TENTACRUEL || \ + BOARD_GOOGLE_VELUZA select RTC select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI @@ -91,6 +93,7 @@ default "Chinchou" if BOARD_GOOGLE_CHINCHOU default "Wugtrio" if BOARD_GOOGLE_WUGTRIO default "Skitty" if BOARD_GOOGLE_SKITTY + default "Veluza" if BOARD_GOOGLE_VELUZA config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index a88be5b..cbe1928 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -34,6 +34,9 @@ config BOARD_GOOGLE_SKITTY bool "-> Skitty" +config BOARD_GOOGLE_VELUZA + bool "-> Veluza" + comment "Staryu" config BOARD_GOOGLE_STARMIE -- To view, visit https://review.coreboot.org/c/coreboot/+/81791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c Gerrit-Change-Number: 81791 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jasper Lee <jasper_lee(a)compal.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shawn Ku <shawnku(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Felix Held (Code Review) 17 Apr '24

17 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... mb/up/squared: Make mini PCIe port mode configurable Add config choice menu and pad configuration to put Mini PCIe port into mSATA mode. The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has been used together with the output of inteltool and intel2pm to deduce the exact pad configuration. Note: the vendor firmware does not autodetect the mode, and the default setting for the port is "Mini PCIe". Tested with Kingston SUV500MS120G mSATA SSD. Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Signed-off-by: Reto Buerki <reet(a)codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80261 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/up/squared/Kconfig M src/mainboard/up/squared/gpio.h M src/mainboard/up/squared/romstage.c 3 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index ca8eef0..628b13e 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -76,4 +76,22 @@ bool default y +choice + prompt "Mini PCIe port mode" + default MINI_PCIE_MODE_PCIE + help + Choose the operating mode of the mini PCIe port. + +config MINI_PCIE_MODE_PCIE + bool "PCIe" + help + Select this option to leave the mini PCIe port in PCIe mode. This is + also the default mode of the vendor firmware. + +config MINI_PCIE_MODE_MSATA + bool "mSATA" + help + Select this option to put the mini PCIe port into mSATA mode. +endchoice + endif diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 1aecc18..876b326 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -777,4 +777,14 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), }; +/* + * Pad configuration to put MiniPCIe port into mSATA mode. + */ +static const struct pad_config msata_mode_gpio_table[] = { + /* ------- GPIO Group North-West ------- */ + + /* GPIO_213 - GPIO */ + PAD_CFG_TERM_GPO(GPIO_213, 0, UP_20K, DEEP), +}; + #endif /* CFG_GPIO_H */ diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 12e4135..f4ccdaf 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -103,6 +103,8 @@ FSP_M_CONFIG *config = &memupd->FspmConfig; gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + if (CONFIG(MINI_PCIE_MODE_MSATA)) + gpio_configure_pads(msata_mode_gpio_table, ARRAY_SIZE(msata_mode_gpio_table)); uint8_t memory_skuid = get_memory_skuid(); printk(BIOS_DEBUG, "MAINBOARD: Found memory SKU ID: 0x%02x\n", memory_skuid); -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 4 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: haswell NRI: Program memory map
by Patrick Rudolph (Code Review) 17 Apr '24

17 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64188?usp=email ) Change subject: haswell NRI: Program memory map ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe Gerrit-Change-Number: 64188 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 17 Apr 2024 13:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: acpigen_ps2_keybd: Add Fn key to linux,keymap
by Paul Menzel (Code Review) 17 Apr '24

17 Apr '24

Attention is currently required from: Aseda Aboagye, Cliff Huang, Lance Zhao, Nick Vaccaro, Shelley Chen, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81895?usp=email ) Change subject: acpigen_ps2_keybd: Add Fn key to linux,keymap ...................................................................... Patch Set 3: (1 comment) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/81895/comment/5d4f7e2e_29605e42 : PS3, Line 22: A value of 0 is ignored. Please also add your explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/81895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c Gerrit-Change-Number: 81895 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 17 Apr 2024 13:31:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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