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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 23: Code-Review+2
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Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/intel/beechnutcity_crb/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/81322/comment/c0f05764_ebd0de2e :
PS12, Line 35: chip superio/common
: device pnp 2e.0 on
: chip superio/aspeed/ast2400
: register "use_espi" = "1"
: device pnp 2e.2 on # SUART1
: io 0x60 = 0x3f8 # PNP_IDX_IO0
: irq 0x70 = 4 # PNP_IDX_IRQ0
: end
: end
: end
: end
: chip drivers/ipmi
: device pnp ca2.0 on end # BMC KCS
: register "wait_for_bmc" = "1"
: register "bmc_boot_timeout" = "60"
: end
> > Sorry, could you please specify? […]
Oh yes, this is needed. Good catch.
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 46:
(4 comments)
File src/soc/intel/xeon_sp/gnr/cpu.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/b0fe637b_919deba9 :
PS45, Line 33: return false;
> Is this correct? I thought firmware (FSP?) switches to untrusted mode at some point. […]
Good catch! Updated.
File src/soc/intel/xeon_sp/gnr/soc_util.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/2d19eb53_6903505f :
PS45, Line 118: printk(BIOS_DEBUG,
: "CXL_NODE_HOB_GUID not found: CXL may not be installed\n");
> nitpick: This looks rather odd, it should fit in one line
Done
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/8290c266_c28c3df7 :
PS45, Line 158: unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current)
: {
: struct device *cpu;
: uint8_t num_cpus = 0;
:
: for (cpu = all_devices; cpu; cpu = cpu->next) {
: if ((cpu->path.type != DEVICE_PATH_APIC)
: || (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
: continue;
: }
: if (!cpu->enabled)
: continue;
: current = acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id);
: num_cpus++;
: }
:
: return current;
: }
> Where did this go?
it is covered by the common codes acpi_arch_fill_madt
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/53bc7d11_645d48eb :
PS45, Line 268: if (CONFIG(SOC_INTEL_HAS_CXL)) {
> Could this change (introducing the `soc_add_dram_resources` function) be split off into a separate c […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/beechnutcity CRB
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
---
A configs/builder/config.intel.crb.bnc
A src/mainboard/intel/beechnutcity_crb/Kconfig
A src/mainboard/intel/beechnutcity_crb/Kconfig.name
A src/mainboard/intel/beechnutcity_crb/Makefile.mk
A src/mainboard/intel/beechnutcity_crb/board.fmd
A src/mainboard/intel/beechnutcity_crb/board_info.txt
A src/mainboard/intel/beechnutcity_crb/bootblock.c
A src/mainboard/intel/beechnutcity_crb/config/iio.c
A src/mainboard/intel/beechnutcity_crb/devicetree.cb
A src/mainboard/intel/beechnutcity_crb/dsdt.asl
A src/mainboard/intel/beechnutcity_crb/ramstage.c
A src/mainboard/intel/beechnutcity_crb/romstage.c
12 files changed, 269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/17
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Change subject: mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
......................................................................
mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
A configs/builder/config.intel.crb.avc
A src/mainboard/intel/avenuecity_crb/Kconfig
A src/mainboard/intel/avenuecity_crb/Kconfig.name
A src/mainboard/intel/avenuecity_crb/Makefile.mk
A src/mainboard/intel/avenuecity_crb/board.fmd
A src/mainboard/intel/avenuecity_crb/board_info.txt
A src/mainboard/intel/avenuecity_crb/bootblock.c
A src/mainboard/intel/avenuecity_crb/config/iio.c
A src/mainboard/intel/avenuecity_crb/devicetree.cb
A src/mainboard/intel/avenuecity_crb/dsdt.asl
A src/mainboard/intel/avenuecity_crb/ramstage.c
A src/mainboard/intel/avenuecity_crb/romstage.c
12 files changed, 269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/40
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,187 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/46
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Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-MessageType: newpatchset