Jean Lucas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82000?usp=email )
Change subject: paylods/edk2: Add Kconfig to use LAPIC timer
......................................................................
paylods/edk2: Add Kconfig to use LAPIC timer
GM45 / Core 2 Duo platforms have issues with HPET. Enable support to use
the LAPIC driver so machines actually boot and don't hang. Tested on a
Lenovo X200.
Change-Id: I33144d6c1c120e7faa47b99e8262b0997c45c9b9
Signed-off-by: Jean Lucas <jean(a)4ray.co>
---
M payloads/external/edk2/Kconfig
M payloads/external/edk2/Makefile
M src/northbridge/intel/gm45/Kconfig
3 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/82000/1
diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig
index 68eb455..e3e00c0 100644
--- a/payloads/external/edk2/Kconfig
+++ b/payloads/external/edk2/Kconfig
@@ -308,6 +308,13 @@
It is needed for AMD Picasso boards with eMMC storage, but will conflict with the
PCI-based eMMC driver, so should only be enabled for AMD Picasso boards.
+config EDK2_USE_LAPIC_TIMER
+ bool "Use LAPIC timer instead of HPET"
+ default n
+ help
+ Select this option to use the LAPIC timer driver instead of HPET. It is needed for GM45
+ platforms which have issues with the HPET on Intel Core 2 Duo.
+
config EDK2_CUSTOM_BUILD_PARAMS
string "edk2 additional custom build parameters"
default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile
index e7f11f0..4cb7f0f 100644
--- a/payloads/external/edk2/Makefile
+++ b/payloads/external/edk2/Makefile
@@ -141,6 +141,10 @@
ifeq ($(CONFIG_EDK2_PCO_MMIO_EMMC),y)
BUILD_STR += -D USE_PCO_MMIO_EMMC=TRUE
endif
+# TIMER_SUPPORT = HPET
+ifeq ($(CONFIG_EDK2_USE_LAPIC_TIMER),y)
+BUILD_STR += -D TIMER_SUPPORT=LAPIC
+endif
endif
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 4fe20ee..baeb209 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -49,4 +49,8 @@
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+config EDK2_USE_LAPIC_TIMER
+ bool
+ default y
+
endif
--
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81958?usp=email )
Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/4335543a_9b3fd741 :
PS1, Line 234: * @param mc_values List of system memory map variables.
> I'll make one desperate last attempt to get this answered... […]
e.g. When SoC codes is adding >4G resources, it might check some conflicts with MMCFG_BASE/LIMIT, e.g. registers defined in 64bit space. These checks are not oriented to create resources, but just refer to them on demands.
Personally I think the developer should be clear to understand what is already created in common codes and what should be created in SoC codes, hence IMO I don't think this will cause obvious error-prone possibilities.
However, from a strict view of API parameter design, it is reasonable to keep minimal parameter lists now and make changes in future. I agree to close the discussion and shorten the parameter list as a solution as of now.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75139?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/asus/p8z77-m: Disable deep sleep
......................................................................
mb/asus/p8z77-m: Disable deep sleep
One can argue whether or not this is desirable, but disabling this means
you cannot use power from the USB ports when the board shuts down, which
is better controlled from an option, but at the very least disabled so
as to replicate default vendor firmware behaviour.
Disable deep sleep like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: I660f2efebf197df055ee7b9c349e4c2b64bda6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75139
Reviewed-by: Keith Hui <buurin(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Keith Hui: Looks good to me, approved
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index ce1eb9e..f7f683b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -81,6 +81,7 @@
device pnp 2e.609 off end # GPIO 6
device pnp 2e.709 off end # GPIO 7
device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
end
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75138?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/asus/p8z77-m: Enable Port 80 UART
......................................................................
mb/asus/p8z77-m: Enable Port 80 UART
Copied this bit from asus/p8z77-m_pro, without it a GRUB2 payload will
get stuck in an endless loop showing
Unknown key 0xff detected
whenever there is an USB device (such as a keyboard) connected.
In this mode GRUB2 is so busy showing this message repeatedly that no
other keypress ever gets handled, and thus no other remedy is possible
than a reset via mb pins and unplugging the USB device.
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: Iebd433e2762a69241257e1b4f859319536a8d8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75138
Reviewed-by: Keith Hui <buurin(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Keith Hui: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index ee2fe9a..ce1eb9e 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -80,6 +80,7 @@
end
device pnp 2e.609 off end # GPIO 6
device pnp 2e.709 off end # GPIO 7
+ device pnp 2e.14 on end # Port 80 UART
end
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM
--
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Change subject: mb/asus/p8z77-m: Enable Port 80 UART
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
i wonder how this fixes the described issue
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81833?usp=email )
Change subject: mb/google/brox/var/greenbayupoc: Add fw_config field for storage
......................................................................
mb/google/brox/var/greenbayupoc: Add fw_config field for storage
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333325006
TEST=emerge-brox coreboot depthcharge with no errors
Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e
Signed-off-by: Eren Peng <peng.eren(a)inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Ivan Chen <yulunchen(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
---
M src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
Derek Huang: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Ivan Chen: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
index e707a9b..ee65135 100644
--- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
@@ -1,3 +1,11 @@
+fw_config
+ field STORAGE 0 1
+ option STORAGE_UNKNOWN 0
+ option STORAGE_UFS 1
+ option STORAGE_NVME 2
+ end
+end
+
chip soc/intel/alderlake
device domain 0 on
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81788?usp=email )
Change subject: acpi: Make acpi_device_write_dsd_gpio() public
......................................................................
acpi: Make acpi_device_write_dsd_gpio() public
Make sure it can be used for other driver.
At present, i2c_generic_write_gpio() is not suitable for being called
by other drivers, so delete it, add acpi_device_write_dsd_gpio() to
replace it, and make it public.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/acpi/device.c
M src/drivers/i2c/generic/generic.c
M src/include/acpi/acpi_device.h
3 files changed, 23 insertions(+), 17 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/acpi/device.c b/src/acpi/device.c
index 95316b0..091a086 100644
--- a/src/acpi/device.c
+++ b/src/acpi/device.c
@@ -39,6 +39,23 @@
#define ACPI_DSD_STORAGE_D3_UUID "5025030F-842F-4AB4-A561-99A5189762D0"
#define ACPI_DSD_STORAGE_D3_NAME "StorageD3Enable"
+/* Write GPIO descriptor of DSD property */
+int acpi_device_write_dsd_gpio(struct acpi_gpio *gpio, int *curr_index)
+{
+ int ret = -1;
+
+ if (!gpio || !curr_index)
+ return ret;
+
+ if (gpio->pin_count == 0)
+ return ret;
+
+ acpi_device_write_gpio(gpio);
+ ret = *curr_index++;
+
+ return ret;
+}
+
/* Write empty word value and return pointer to it */
static void *acpi_device_write_zero_len(void)
{
diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c
index afff978..a2d510b 100644
--- a/src/drivers/i2c/generic/generic.c
+++ b/src/drivers/i2c/generic/generic.c
@@ -27,20 +27,6 @@
return true;
}
-static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index)
-{
- int ret = -1;
-
- if (gpio->pin_count == 0)
- return ret;
-
- acpi_device_write_gpio(gpio);
- ret = *curr_index;
- (*curr_index)++;
-
- return ret;
-}
-
void i2c_generic_fill_ssdt(const struct device *dev,
void (*callback)(const struct device *dev),
struct drivers_i2c_generic_config *config)
@@ -96,15 +82,15 @@
/* Use either Interrupt() or GpioInt() */
if (config->irq_gpio.pin_count)
- irq_gpio_index = i2c_generic_write_gpio(&config->irq_gpio,
+ irq_gpio_index = acpi_device_write_dsd_gpio(&config->irq_gpio,
&curr_index);
else
acpi_device_write_interrupt(&config->irq);
if (i2c_generic_add_gpios_to_crs(config) == true) {
- reset_gpio_index = i2c_generic_write_gpio(&config->reset_gpio,
+ reset_gpio_index = acpi_device_write_dsd_gpio(&config->reset_gpio,
&curr_index);
- enable_gpio_index = i2c_generic_write_gpio(&config->enable_gpio,
+ enable_gpio_index = acpi_device_write_dsd_gpio(&config->enable_gpio,
&curr_index);
}
acpigen_write_resourcetemplate_footer();
diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h
index 9ce5e0a..3b66989 100644
--- a/src/include/acpi/acpi_device.h
+++ b/src/include/acpi/acpi_device.h
@@ -313,6 +313,9 @@
/* Write I2cSerialBus() descriptor to SSDT AML output */
void acpi_device_write_i2c(const struct acpi_i2c *i2c);
+/* Write GPIO descriptor of DSD property */
+int acpi_device_write_dsd_gpio(struct acpi_gpio *gpio, int *curr_index);
+
/*
* ACPI SPI Bus
*/
--
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Change subject: device_util: Handle domain device in dev_get_domain
......................................................................
Patch Set 3: Code-Review+2
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