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Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,185 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/48
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Hello Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
soc/intel/xeon_sp: Add soc_add_dram_resources
SoC specific DRAM resource, e.g. 4GB above DRAM memory map, CXL,
et al, are different across SoC generations. This patch separates
the codes so that different SoC generations could have different
implementations.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 87 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/3
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 38:
(2 comments)
File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/5a7c1e1e_e8877b10 :
PS31, Line 10: #include <efi/efi_datatype.h>
> I removed this and tried. Didn't face any issues. Removing from the patch.
Done
File src/include/efi/efi_datatype.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/e8f6475e_b6362281 :
PS30, Line 19: #define EFIAPI __attribute__((__ms_abi__))
> > Added to EDK2 headers and tried. It is working fine. https://review.coreboot. […]
Acknowledged
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Lookiing at the jenkins log this doesnt actually build:
src/mainboard/dell/optiplex_9020/mainboard.c: In function 'sch5555_ec_hwm_init':
src/mainboard/dell/optiplex_9020/mainboard.c:380:26: error: comparison is always false due to limited range of data type [-Werror=type-limits]
380 | if (chassis_type == -1 || get_uint_option("fan_full_speed", 0)) {
type of chassis_type and return type of get_chassis_type() needs to be fixed
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/9d026983_d15a03c7 :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> Why? If there's a failure, logging the failures here will spam the coreboot log. […]
Looks like Máté replied in the meantime. I don't know if this comment was resolved, but given our replies I'll mark it as such.
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/4628c5d9_82a16cfc :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> Understood. The failure case should still be handled, if retry = 0xfff, and an error logged.
Why? If there's a failure, logging the failures here will spam the coreboot log. These functions are used very often.
It's very unlikely that the retry limit will get reached in practice, unless the chip is outright dead. If anything, one might check if the chip is responding early on and bail out if that's not the case.
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/4ea8b766_6bb0dd3c :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> Understood. The failure case should still be handled, if retry = 0xfff, and an error logged.
The vendor firmware doesn't do that either, and no one has ever seen this failure mode on this hardware. I don't think that it is really necessary to add code for this.
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/ec2f4f3e_3fee0a27 :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> Maybe `retry` would be a more descriptive name?
Understood. The failure case should still be handled, if retry = 0xfff, and an error logged.
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Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email )
Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
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Patch Set 6:
(2 comments)
File src/mainboard/dell/optiplex_9020/mainboard.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/0f3802c2_8da6e256 :
PS6, Line 32: struct hwm_tab_entry HWM_TAB3[] = {
> Looks like they were extracted as-is from vendor firmware.
These were produced to match the values programmed by the vendor firmware.
These are a purely factual description of the fan control profiles.
All the actual logic is embedded in the EC.
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/fec83446_76cdb3b8 :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> There's no time delay in this code. […]
Perhaps "timeout" as a loop counter is slightly misleading.
Having no actual delay here is intended, this code is meant to poll the specific I/O port until the EC ACKs the message. This usually happens in <20 iterations.
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