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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/dell/optiplex_9020/mainboard.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/94ec1228_f4c6a2d6 :
PS6, Line 32: struct hwm_tab_entry HWM_TAB3[] = {
> How did you generate these “tables”?
Looks like they were extracted as-is from vendor firmware.
File src/mainboard/dell/optiplex_9020/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/81529/comment/ef851f10_978fbc53 :
PS6, Line 25: for (size_t timeout = 0; timeout < 0xfff; ++timeout)
> Use `wait_ms()` from coreboot’s timestamp framework?
There's no time delay in this code. It just retries a bunch of times, limited by the time it takes for the I/O read to complete. See https://review.coreboot.org/c/coreboot/+/81529/comment/5add389b_b100fd0a/ for more details.
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/074b7c8a_68e28961 :
PS1, Line 306: } else {
> @angel GNR/Birch stream is Gen 6, and the code is published in the patch train.
@Sheng https://review.coreboot.org/c/coreboot/+/81316/47/src/soc/intel/xeon_sp/chi… is the current implementation for Gen6:
```
/*
* Add SoC specific DRAM resources
*
* @param dev Pointer of the device to add resource on.
* @param mc_values List of system memory map variables.
* @param index Pointer of the largest resource index, which will be updated by this function.
*/
void soc_add_dram_resources(struct device *dev, uint64_t mc_values[], int *index)
{
//TODO: not implemented yet
}
```
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Change subject: util/cbfstool: Add --64 option for 64-bit payload stitching
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h:
https://review.coreboot.org/c/coreboot/+/81964/comment/27c4c4f1_230b1684 :
PS2, Line 144: /* 1 for 64-bit payload. 0 for 32-bit payload. */
: uint32_t payload_64_bit;
payload_64_bit is used as boot in util/cbfstool/cbfstool.c file.
Please why payload_64_bit is declared as uint32_t here ?
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/19dfd9ff_4653e057 :
PS1, Line 306: } else {
> For now, as the implementation for GEN6 CPUs is not yet implemented (at least not publicly), I belie […]
@angel GNR/Birch stream is Gen 6, and the code is published in the patch train.
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Hello Angel Pons, Jason Glenesk, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81999?usp=email
to look at the new patch set (#5).
Change subject: Documentation/releases: Add coreboot-24.xx-relnotes
......................................................................
Documentation/releases: Add coreboot-24.xx-relnotes
Add a template in preparation for the next upcoming release.
This template is based on coreboot-24.05-relnotes.
Change-Id: I35039bd0af8c6f199cd5ad10d13780376f371bd5
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
A Documentation/releases/coreboot-24.xx-relnotes.md
1 file changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/81999/5
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