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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/dc5fe671_18b6488f :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> ARM did what they have promissed: https://developer.arm.com/documentation/den0044/latest. […]
Done
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 18: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/0ea77edd_6d4fe33d :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> Then let's keep this thread unresolved until this is done.
ARM did what they have promissed: https://developer.arm.com/documentation/den0044/latest.
I will set this comment as resolved now and merge this patch within 24 hours if there are no further objections.
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Change subject: util/lint: Add lint rule to watch for Makefile.inc
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/framework: Initial push of azalea (Framework 13 AMD 7040)
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/framework/azalea/board_info.txt:
https://review.coreboot.org/c/coreboot/+/81978/comment/90685833_cbf3c103 :
PS5, Line 2: Board name: Azalea (13" AMD Ryzen 4070)
Typo, 7040*
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > > https://review.coreboot.org/c/coreboot/+/82016 implements a 32bit entry point that sets up paging in 64bit libpayload. Untested. If it works, it should work without modifying coreboot.
> >
> > Thanks for the CL, just wondering if the direction check is still valid (basically the one that you have set a day before)?
> >
> > - Add a 64bit entry (maybe call it x86_long_mode, to avoid confusion?) in cbfs_payload_segment_type: maybe PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY ?
> >
> > * CB:81964
> >
> > Add a way to cbfstool to mark the entry of the payload as such (similar to your --64 patch, but then not with file attr, but as payload segment)
> >
> > * CB:81964
> >
> > 64bit ramstage coreboot at runtime decides to jump to PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY directly if found
> >
> > * CB:81960
> >
> > If not found keep the old 32bit entering code
> >
> > * CB:81960
> >
> > If above direction is still valid then wondering why we are again discussing about ` Untested. If it works, it should work without modifying coreboot.`
> >
> > Please let me know if you prefer to not make any change in coreboot for launching 64-bit payload directly even after setting the direction above?
> >
> > I'm aware about head.S change to switch from protected to long mode after entering into the payload in 32bit mode. But as discussion previosuly, we wish to follow pure-64 flow going forward for next generation Intel platform hence, prefers to jump into 64-bit w/o trunking.
>
> it may be good direction going forward where we are allowing provision of multiple entry point (both 32-bit and 64-bit) and give the flexibility to coreboot launch the desire entrypoint.
btw, thanks for https://review.coreboot.org/c/coreboot/+/82016/1/payloads/libpayload/driver… change. I have missed this in my CL.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81968?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: libpayload: Add initial patch or 64-bit compilation
......................................................................
libpayload: Add initial patch or 64-bit compilation
Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.mk
A payloads/libpayload/arch/x64/Kconfig
A payloads/libpayload/arch/x64/Makefile.mk
A payloads/libpayload/arch/x64/apic.c
A payloads/libpayload/arch/x64/boot_media.c
A payloads/libpayload/arch/x64/cache.c
A payloads/libpayload/arch/x64/coreboot.c
A payloads/libpayload/arch/x64/delay.c
A payloads/libpayload/arch/x64/exception.c
A payloads/libpayload/arch/x64/exception_asm.S
A payloads/libpayload/arch/x64/exec.S
A payloads/libpayload/arch/x64/gdb.c
A payloads/libpayload/arch/x64/head.S
A payloads/libpayload/arch/x64/libpayload.ldscript
A payloads/libpayload/arch/x64/main.c
A payloads/libpayload/arch/x64/multiboot.c
A payloads/libpayload/arch/x64/selfboot.c
A payloads/libpayload/arch/x64/string.c
A payloads/libpayload/arch/x64/sysinfo.c
A payloads/libpayload/arch/x64/timer.c
A payloads/libpayload/arch/x64/util.S
A payloads/libpayload/arch/x64/virtual.c
M payloads/libpayload/arch/x86/Kconfig
M payloads/libpayload/bin/lpgcc
M payloads/libpayload/drivers/storage/ahci_common.c
M payloads/libpayload/drivers/usb/uhci.c
A payloads/libpayload/include/x64/arch/apic.h
A payloads/libpayload/include/x64/arch/barrier.h
A payloads/libpayload/include/x64/arch/cache.h
A payloads/libpayload/include/x64/arch/cpuid.h
A payloads/libpayload/include/x64/arch/exception.h
A payloads/libpayload/include/x64/arch/io.h
A payloads/libpayload/include/x64/arch/msr.h
A payloads/libpayload/include/x64/arch/rdtsc.h
A payloads/libpayload/include/x64/arch/types.h
A payloads/libpayload/include/x64/arch/virtual.h
M payloads/libpayload/vboot/Makefile.mk
39 files changed, 3,109 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81968/4
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > https://review.coreboot.org/c/coreboot/+/82016 implements a 32bit entry point that sets up paging in 64bit libpayload. Untested. If it works, it should work without modifying coreboot.
>
> Thanks for the CL, just wondering if the direction check is still valid (basically the one that you have set a day before)?
>
> - Add a 64bit entry (maybe call it x86_long_mode, to avoid confusion?) in cbfs_payload_segment_type: maybe PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY ?
>
> * CB:81964
>
> Add a way to cbfstool to mark the entry of the payload as such (similar to your --64 patch, but then not with file attr, but as payload segment)
>
> * CB:81964
>
> 64bit ramstage coreboot at runtime decides to jump to PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY directly if found
>
> * CB:81960
>
> If not found keep the old 32bit entering code
>
> * CB:81960
>
> If above direction is still valid then wondering why we are again discussing about ` Untested. If it works, it should work without modifying coreboot.`
>
> Please let me know if you prefer to not make any change in coreboot for launching 64-bit payload directly even after setting the direction above?
>
> I'm aware about head.S change to switch from protected to long mode after entering into the payload in 32bit mode. But as discussion previosuly, we wish to follow pure-64 flow going forward for next generation Intel platform hence, prefers to jump into 64-bit w/o trunking.
it may be good direction going forward where we are allowing provision of multiple entry point (both 32-bit and 64-bit) and give the flexibility to coreboot launch the desire entrypoint.
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Change subject: util/lint: Add lint rule to watch for Makefile.inc
......................................................................
Patch Set 3:
(1 comment)
File util/lint/lint-stable-030-makefile-inc:
https://review.coreboot.org/c/coreboot/+/81857/comment/1532c8d1_eff92998 :
PS2, Line 22:
> Use spaces instead of tabs for consistency
Done
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> https://review.coreboot.org/c/coreboot/+/82016 implements a 32bit entry point that sets up paging in 64bit libpayload. Untested. If it works, it should work without modifying coreboot.
Thanks for the CL, just wondering if the direction check is still valid (basically the one that you have set a day before)?
- Add a 64bit entry (maybe call it x86_long_mode, to avoid confusion?) in cbfs_payload_segment_type: maybe PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY ?
* CB:81964
Add a way to cbfstool to mark the entry of the payload as such (similar to your --64 patch, but then not with file attr, but as payload segment)
* CB:81964
64bit ramstage coreboot at runtime decides to jump to PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY directly if found
* CB:81960
If not found keep the old 32bit entering code
* CB:81960
If above direction is still valid then wondering why we are again discussing about ` Untested. If it works, it should work without modifying coreboot.`
Please let me know if you prefer to not make any change in coreboot for launching 64-bit payload directly even after setting the direction above?
I'm aware about head.S change to switch from protected to long mode after entering into the payload in 32bit mode. But as discussion previosuly, we wish to follow pure-64 flow going forward for next generation Intel platform hence, prefers to jump into 64-bit w/o trunking.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81960?usp=email )
Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 4:
(1 comment)
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/ed689899_d9adc674 :
PS3, Line 47: is_payload_64_bit_enabled
> I'd assume a call to die() or assembly code to set up long mode before jumping to payload.
sorry, unable to follow your comment. Are you wondering what if the long more entry point is not enabled and coreboot is marking a call into it? if so, CB:81968 has added the long mode entry point.
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