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Change subject: util/cbfstool: Add `PL64` segment for payload
......................................................................
Patch Set 3:
(3 comments)
Patchset:
PS1:
> > > > > > Why not parse the ELF for architecture? […]
Acknowledged
File src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h:
https://review.coreboot.org/c/coreboot/+/81964/comment/7735cc00_2570275d :
PS2, Line 144: /* 1 for 64-bit payload. 0 for 32-bit payload. */
: uint32_t payload_64_bit;
> payload_64_bit is used as boot in util/cbfstool/cbfstool.c file. […]
Acknowledged
File util/cbfstool/cbfstool.c:
https://review.coreboot.org/c/coreboot/+/81964/comment/3646e57d_bddbe3c1 :
PS2, Line 2006: 64
> has an x86_64 entry point
Acknowledged
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Hello Arthur Heymans, Julius Werner, Jérémy Compostella, Kapil Porwal, build bot (Jenkins),
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
arch/x86: Enable long mode entry into payload for x86_64 support
This patch allows coreboot to enter libpayload in long mode (64-bit)
instead of protected mode (32-bit), enabling support for upcoming Intel
platforms and payloads requiring access to memory beyond 4GB.
This change ensures compatibility between libpayload and depthcharge,
preventing compilation issues and stack misalignment during the
transition.
BUG=b:242829490
TEST=Entered libpayload in long mode, successfully parsed coreboot
table.
Change-Id: Ic5e6f0af11c05e8b075b8c20880c012747a1df9b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/arch/x86/boot.c
1 file changed, 61 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81960/4
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Hello Julius Werner, build bot (Jenkins),
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Change subject: util/cbfstool: Add `PL64` segment for payload
......................................................................
util/cbfstool: Add `PL64` segment for payload
This patch adds `PL64` segment if below conditions are being met
* Payload with x86_64 support enabled.
* Payload has 64-bit entry point
* Injects the PAYLOAD_SEGMENT_X86_LONG_MODE_ENTRY/"PL64" segment into the payload.
This allows direct long mode jumps into the payload if supported,
otherwise falling back to protected mode. Existing 32-bit payload
behavior remains unchanged.
BUG=b:242829490
TEST=Able to verify "PL64" signature at the payload while
building the payload using x86_64.
Change-Id: I41562041d6c09869c7966ea31503f002ca1caefa
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
M util/cbfstool/cbfs-mkpayload.c
2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81964/3
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Change subject: arch/arm64: Implement initial set of SMBIOS tables
......................................................................
Patch Set 15:
(1 comment)
File src/arch/arm64/smbios.c:
https://review.coreboot.org/c/coreboot/+/78285/comment/87048053_e80298df :
PS3, Line 50: void __weak smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count)
> Okay, yeah, I agree you don't want to do full SMP setup here. […]
Since we can't guarantee that walking the FDT is the right approach in all cases, since TF-A has no formal spec that I know of (and TF-A-as-BL1 is only one path, not architecturally guaranteed), I'm just dropping this function.
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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
Patch Set 15:
(1 comment)
File src/arch/arm64/include/armv8/arch/smc.h:
https://review.coreboot.org/c/coreboot/+/78284/comment/4ebc36e1_5b8458c0 :
PS13, Line 8: static inline u
> Sorry, this one can't be static inline. […]
Oh, I see. I thought that I could forward the declaration on to the assembly, and it would inline that into the caller. Although maybe that doesn't make sense after all, since the assembly function is its own symbol. My mistake.
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Change subject: arch/arm64: Implement initial set of SMBIOS tables
......................................................................
arch/arm64: Implement initial set of SMBIOS tables
Implement the two architectural tables: processor and cache.
Note that SoC/board code should override core-thread count
and, for spec-compliance, create CBMEM_ID_MEMINFO.
Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15
Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
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M src/include/smbios.h
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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
arch/arm64: Support calling a trusted monitor
Implement support for generating an SMC to call a trusted monitor. Some
functions are provided to read the SoC ID from the monitor, if
supported.
Change-Id: I158db0b971aba722b3995d52162146aa406d1644
Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
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A src/arch/arm64/smc_asm.S
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Change subject: arch/arm64: Implement initial set of SMBIOS tables
......................................................................
arch/arm64: Implement initial set of SMBIOS tables
Implement the two architectural tables: processor and cache.
Note that SoC/board code should override core-thread count
and, for spec-compliance, create CBMEM_ID_MEMINFO.
Need to confirm tables are in fact compliant.
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---
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M src/arch/arm64/tables.c
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4 files changed, 233 insertions(+), 1 deletion(-)
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Change subject: arch/arm64: Support calling a trusted monitor
......................................................................
arch/arm64: Support calling a trusted monitor
Implement support for generating an SMC to call a trusted monitor. Some
functions are provided to read the SoC ID from the monitor, if
supported.
Change-Id: I158db0b971aba722b3995d52162146aa406d1644
Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
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A src/arch/arm64/smc_asm.S
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81354/comment/9d795591_be84de34 :
PS4, Line 24: TEST=emerge-${BOARD} coreboot then check ACPI table on DUT
Please document the commands how to check for the relevant things.
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