coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81379?usp=email ) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:14:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81410?usp=email ) Change subject: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81410/comment/92e62295_d70cdda8 : PS1, Line 10: Provide a Kconfig variable, default y, to enable it. > What happens if it's enabled but not present in the chip vs if it's present but disabled? Is this de […] that's why it's not interactive. If it's enabled in the binary, but not enabled in the part, you'll get a fault. There are very few parts that do not have it IIUC, it went in a while ago. The printf is a placeholder for hug's code. You're right, it changes the binary, what am I thinking. Patchset: PS1: > Why wouldn't this change the binary? You're adding code. […] yeah, you're right. I wonder if it's best to yank out the code change for now? File src/arch/riscv/payload.c: https://review.coreboot.org/c/coreboot/+/81410/comment/4e1e4f8f_acc006de : PS1, Line 72: part > Nit: Chip? SOC? […] I like that. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/81410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 Gerrit-Change-Number: 81410 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:13:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/docker/: Drop recommonmark pip module
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80313?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/docker/: Drop recommonmark pip module ...................................................................... util/docker/: Drop recommonmark pip module The documentation is now built using MyST Parser, so Recommonmark can be dropped. Change-Id: I7f6810c9429573c0c51d3d72b36e9fc2ae2185f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80313 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-jenkins-node/Dockerfile M util/docker/doc.coreboot.org/Dockerfile 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index d1a5de9..51a4b27 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -78,7 +78,6 @@ pip3 install --no-cache-dir \ setuptools==58.2.0 \ jinja2==3.1.3 \ - recommonmark===0.7.1 \ myst-parser===2.0.0 \ sphinx===7.2.6 \ sphinxcontrib-ditaa===1.0.2 \ diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index d0c32c9..3f28c83 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -14,7 +14,6 @@ pip3 install --upgrade --no-cache-dir pip && \ pip3 install --no-cache-dir \ jinja2==3.1.3 \ - recommonmark===0.7.1 \ myst-parser==2.0.0 \ sphinx===7.2.6 \ sphinxcontrib-ditaa===1.0.2 \ -- To view, visit https://review.coreboot.org/c/coreboot/+/80313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f6810c9429573c0c51d3d72b36e9fc2ae2185f5 Gerrit-Change-Number: 80313 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[main]: Docs: Replace Recommonmark with MyST Parser
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73158?usp=email ) Change subject: Docs: Replace Recommonmark with MyST Parser ...................................................................... Docs: Replace Recommonmark with MyST Parser Recommonmark has been deprecated since 2021 [1] and the last release was over 3 years ago [2]. As per their announcement, Markedly Structured Text (MyST) Parser [3] is the recommended replacement. For the most part, the existing documentation is compatible with MyST, as both parsers are built around the CommonMark flavor of Markdown. The main difference that affects coreboot is how the Sphinx toctree is generated. Recommonmark has a feature called auto_toc_tree, which converts single level lists of references into a toctree: * [Part 1: Starting from scratch](part1.md) * [Part 2: Submitting a patch to coreboot.org](part2.md) * [Part 3: Writing unit tests](part3.md) * [Managing local additions](managing_local_additions.md) * [Flashing firmware](flashing_firmware/index.md) MyST Parser does not provide a replacement for this feature, meaning the toctree must be defined manually. This is done using MyST's syntax for Sphinx directives: ```{toctree} :maxdepth: 1 Part 1: Starting from scratch <part1.md> Part 2: Submitting a patch to coreboot.org <part2.md> Part 3: Writing unit tests <part3.md> Managing local additions <managing_local_additions.md> Flashing firmware <flashing_firmware/index.md> ``` Internally, auto_toc_tree essentially converts lists of references into the Sphinx toctree structure that the MyST syntax above more directly represents. The toctrees were converted to the MyST syntax using the following command and Python script: `find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py` ``` import re import sys in_list = False f = open(sys.argv[1]) lines = f.readlines() f.close() with open(sys.argv[1], "w") as f: for line in lines: match = re.match(r"^[-*+] \[(.*)\]$(.*)$$", line) if match is not None: if not in_list: in_list = True f.write("```{toctree}\n") f.write(":maxdepth: 1\n\n") f.write(match.group(1) + " <" + match.group(2) + ">\n") else: if in_list: f.write("```\n") f.write(line) in_list = False if in_list: f.write("```\n") ``` While this does add a little more work for creating the toctree, this does give more control over exactly what goes into the toctree. For instance, lists of links to external resources currently end up in the toctree, but we may want to limit it to pages within coreboot. This change does break rendering and navigation of the documentation in applications that can render Markdown, such as Okular, Gitiles, or the GitHub mirror. Assuming the docs are mainly intended to be viewed after being rendered to doc.coreboot.org, this is probably not an issue in practice. Another difference is that MyST natively supports Markdown tables, whereas with Recommonmark, tables had to be written in embedded rST [4]. However, MyST also supports embedded rST, so the existing tables can be easily converted as the syntax is nearly identical. These were converted using `find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"` Makefile.sphinx and conf.py were regenerated from scratch by running `sphinx-quickstart` using the updated version of Sphinx, which removes a lot of old commented out boilerplate. Any relevant changes coreboot had made on top of the previous autogenerated versions of these files were ported over to the newly generated file. From some initial testing the generated webpages appear and function identically to the existing documentation built with Recommonmark. TEST: `make -C util/docker docker-build-docs` builds the documentation successfully and the generated output renders properly when viewed in a web browser. [1] https://github.com/readthedocs/recommonmark/issues/221 [2] https://pypi.org/project/recommonmark/ [3] https://myst-parser.readthedocs.io/en/latest/ [4] https://doc.coreboot.org/getting_started/writing_documentation.html Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/Makefile.sphinx M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/arch/index.md M Documentation/arch/x86/index.md M Documentation/community/index.md M Documentation/conf.py M Documentation/contributing/index.md M Documentation/drivers/index.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/build_system.md M Documentation/getting_started/gpio.md M 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Documentation/mainboard/purism/librem_mini.md M Documentation/mainboard/starlabs/labtop_cml.md M Documentation/mainboard/starlabs/labtop_kbl.md M Documentation/mainboard/starlabs/lite_glk.md M Documentation/mainboard/starlabs/lite_glkr.md M Documentation/mainboard/starlabs/starbook_adl.md M Documentation/mainboard/starlabs/starbook_tgl.md M Documentation/mainboard/supermicro/x10slm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md M Documentation/mainboard/supermicro/x9sae.md M Documentation/mainboard/system76/addw1.md M Documentation/mainboard/system76/addw2.md M Documentation/mainboard/system76/addw3.md M Documentation/mainboard/system76/bonw14.md M Documentation/mainboard/system76/bonw15.md M Documentation/mainboard/system76/darp6.md M Documentation/mainboard/system76/darp7.md M Documentation/mainboard/system76/darp8.md M Documentation/mainboard/system76/darp9.md M Documentation/mainboard/system76/galp4.md M Documentation/mainboard/system76/galp5.md M Documentation/mainboard/system76/galp6.md M Documentation/mainboard/system76/galp7.md M Documentation/mainboard/system76/gaze15.md M Documentation/mainboard/system76/gaze16.md M Documentation/mainboard/system76/gaze17.md M Documentation/mainboard/system76/gaze18.md M Documentation/mainboard/system76/lemp10.md M Documentation/mainboard/system76/lemp11.md M Documentation/mainboard/system76/lemp12.md M Documentation/mainboard/system76/lemp9.md M Documentation/mainboard/system76/oryp10.md M Documentation/mainboard/system76/oryp11.md M Documentation/mainboard/system76/oryp5.md M Documentation/mainboard/system76/oryp6.md M Documentation/mainboard/system76/oryp7.md M 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Documentation/releases/coreboot-4.20.1-relnotes.md M Documentation/releases/coreboot-4.21-relnotes.md M Documentation/releases/coreboot-4.22-relnotes.md M Documentation/releases/index.md M Documentation/releases/templates.md M Documentation/security/index.md M Documentation/security/memory_clearing.md M Documentation/security/vboot/index.md M Documentation/soc/amd/index.md M Documentation/soc/amd/psp_integration.md M Documentation/soc/cavium/cn81xx/index.md M Documentation/soc/cavium/index.md M Documentation/soc/index.md M Documentation/soc/intel/broadwell/index.md M Documentation/soc/intel/code_development_model/code_development_model.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/index.md M Documentation/soc/intel/fsp/ppi/mp_service_ppi.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/soc/intel/index.md M Documentation/soc/intel/mp_init/mp_init.md M Documentation/soc/intel/xeon_sp/index.md M Documentation/soc/qualcomm/index.md M Documentation/superio/index.md M Documentation/superio/nuvoton/npcd378.md M Documentation/technotes/asan.md M Documentation/technotes/console.md M Documentation/technotes/index.md M Documentation/tutorial/flashing_firmware/index.md M Documentation/tutorial/index.md M Documentation/tutorial/part3.md M Documentation/util.md M Documentation/util/cbfstool/index.md M Documentation/util/ifdtool/index.md M Documentation/util/ifdtool/layout.md M Documentation/vendorcode/cavium/index.md M Documentation/vendorcode/eltan/index.md M Documentation/vendorcode/index.md 178 files changed, 1,261 insertions(+), 1,021 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/Makefile.sphinx b/Documentation/Makefile.sphinx index 289c45b..c4984ec 100644 --- a/Documentation/Makefile.sphinx +++ b/Documentation/Makefile.sphinx @@ -1,60 +1,20 @@ ## SPDX-License-Identifier: GPL-2.0-only -# Makefile for Sphinx documentation +# Minimal makefile for Sphinx documentation # -# You can set these variables from the command line. -SPHINXOPTS ?= -SPHINXBUILD = sphinx-build -SPHINXAUTOBUILD = sphinx-autobuild -PAPER = -BUILDDIR = _build +# You can set these variables from the command line, and also +# from the environment for the first two. +SPHINXOPTS ?= +SPHINXBUILD ?= sphinx-build +SPHINXAUTOBUILD = sphinx-autobuild +SOURCEDIR = . +BUILDDIR = _build -# Internal variables. -PAPEROPT_a4 = -D latex_paper_size=a4 -PAPEROPT_letter = -D latex_paper_size=letter -ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . -# the i18n builder cannot share the environment and doctrees with the others -I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . - -.PHONY: help +# Put it first so that "make" without argument is like "make help". help: - @echo "Please use \`make <target>' where <target> is one of" - @echo " html to make standalone HTML files" - @echo " dirhtml to make HTML files named index.html in directories" - @echo " singlehtml to make a single large HTML file" - @echo " pickle to make pickle files" - @echo " json to make JSON files" - @echo " htmlhelp to make HTML files and a HTML help project" - @echo " qthelp to make HTML files and a qthelp project" - @echo " applehelp to make an Apple Help Book" - @echo " devhelp to make HTML files and a Devhelp project" - @echo " epub to make an epub" - @echo " epub3 to make an epub3" - @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter" - @echo " latexpdf to make LaTeX files and run them through pdflatex" - @echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx" - @echo " text to make text files" - @echo " man to make manual pages" - @echo " texinfo to make Texinfo files" - @echo " info to make Texinfo files and run them through makeinfo" - @echo " gettext to make PO message catalogs" - @echo " changes to make an overview of all changed/added/deprecated items" - @echo " xml to make Docutils-native XML files" - @echo " pseudoxml to make pseudoxml-XML files for display purposes" - @echo " linkcheck to check all external links for integrity" - @echo " doctest to run all doctests embedded in the documentation (if enabled)" - @echo " coverage to run coverage check of the documentation (if enabled)" - @echo " dummy to check syntax errors of document sources" + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) -.PHONY: clean -clean: - rm -rf $(BUILDDIR) - -.PHONY: html -html: - $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html - @echo - @echo "Build finished. The HTML pages are in $(BUILDDIR)/html." +.PHONY: help Makefile.sphinx .PHONY: livehtml livehtml: @@ -63,172 +23,7 @@ @echo $(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR) -.PHONY: dirhtml -dirhtml: - $(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml - @echo - @echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml." - -.PHONY: singlehtml -singlehtml: - $(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml - @echo - @echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml." - -.PHONY: pickle -pickle: - $(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle - @echo - @echo "Build finished; now you can process the pickle files." - -.PHONY: json -json: - $(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json - @echo - @echo "Build finished; now you can process the JSON files." - -.PHONY: htmlhelp -htmlhelp: - $(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp - @echo - @echo "Build finished; now you can run HTML Help Workshop with the" \ - ".hhp project file in $(BUILDDIR)/htmlhelp." - -.PHONY: qthelp -qthelp: - $(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp - @echo - @echo "Build finished; now you can run "qcollectiongenerator" with the" \ - ".qhcp project file in $(BUILDDIR)/qthelp, like this:" - @echo "# qcollectiongenerator $(BUILDDIR)/qthelp/coreboot.qhcp" - @echo "To view the help file:" - @echo "# assistant -collectionFile $(BUILDDIR)/qthelp/coreboot.qhc" - -.PHONY: applehelp -applehelp: - $(SPHINXBUILD) -b applehelp $(ALLSPHINXOPTS) $(BUILDDIR)/applehelp - @echo - @echo "Build finished. The help book is in $(BUILDDIR)/applehelp." - @echo "N.B. You won't be able to view it unless you put it in" \ - "~/Library/Documentation/Help or install it in your application" \ - "bundle." - -.PHONY: devhelp -devhelp: - $(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp - @echo - @echo "Build finished." - @echo "To view the help file:" - @echo "# mkdir -p $$HOME/.local/share/devhelp/coreboot" - @echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/coreboot" - @echo "# devhelp" - -.PHONY: epub -epub: - $(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub - @echo - @echo "Build finished. The epub file is in $(BUILDDIR)/epub." - -.PHONY: epub3 -epub3: - $(SPHINXBUILD) -b epub3 $(ALLSPHINXOPTS) $(BUILDDIR)/epub3 - @echo - @echo "Build finished. The epub3 file is in $(BUILDDIR)/epub3." - -.PHONY: latex -latex: - $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex - @echo - @echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex." - @echo "Run \`make' in that directory to run these through (pdf)latex" \ - "(use \`make latexpdf' here to do that automatically)." - -.PHONY: latexpdf -latexpdf: - $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex - @echo "Running LaTeX files through pdflatex..." - $(MAKE) -C $(BUILDDIR)/latex all-pdf - @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex." - -.PHONY: latexpdfja -latexpdfja: - $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex - @echo "Running LaTeX files through platex and dvipdfmx..." - $(MAKE) -C $(BUILDDIR)/latex all-pdf-ja - @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex." - -.PHONY: text -text: - $(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text - @echo - @echo "Build finished. The text files are in $(BUILDDIR)/text." - -.PHONY: man -man: - $(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man - @echo - @echo "Build finished. The manual pages are in $(BUILDDIR)/man." - -.PHONY: texinfo -texinfo: - $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo - @echo - @echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo." - @echo "Run \`make' in that directory to run these through makeinfo" \ - "(use \`make info' here to do that automatically)." - -.PHONY: info -info: - $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo - @echo "Running Texinfo files through makeinfo..." - make -C $(BUILDDIR)/texinfo info - @echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo." - -.PHONY: gettext -gettext: - $(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale - @echo - @echo "Build finished. The message catalogs are in $(BUILDDIR)/locale." - -.PHONY: changes -changes: - $(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes - @echo - @echo "The overview file is in $(BUILDDIR)/changes." - -.PHONY: linkcheck -linkcheck: - $(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck - @echo - @echo "Link check complete; look for any errors in the above output " \ - "or in $(BUILDDIR)/linkcheck/output.txt." - -.PHONY: doctest -doctest: - $(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest - @echo "Testing of doctests in the sources finished, look at the " \ - "results in $(BUILDDIR)/doctest/output.txt." - -.PHONY: coverage -coverage: - $(SPHINXBUILD) -b coverage $(ALLSPHINXOPTS) $(BUILDDIR)/coverage - @echo "Testing of coverage in the sources finished, look at the " \ - "results in $(BUILDDIR)/coverage/python.txt." - -.PHONY: xml -xml: - $(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml - @echo - @echo "Build finished. The XML files are in $(BUILDDIR)/xml." - -.PHONY: pseudoxml -pseudoxml: - $(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml - @echo - @echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml." - -.PHONY: dummy -dummy: - $(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy - @echo - @echo "Build finished. Dummy builder generates no files." +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile.sphinx + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md index f9ae425..15d3ddd 100644 --- a/Documentation/acpi/index.md +++ b/Documentation/acpi/index.md @@ -5,18 +5,34 @@ upwards. -- [SSDT UID generation](uid.md) +```{toctree} +:maxdepth: 1 + +SSDT UID generation <uid.md> +``` ## GPIO -- [GPIO toggling in ACPI AML](gpio.md) +```{toctree} +:maxdepth: 1 + +GPIO toggling in ACPI AML <gpio.md> +``` ## Windows-specific ACPI documentation -- [Windows-specific documentation](windows.md) +```{toctree} +:maxdepth: 1 + +Windows-specific documentation <windows.md> +``` ## ACPI specification - Useful links -- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html) -- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbo… -- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.h… +```{toctree} +:maxdepth: 1 + +ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html> +ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-oper…> +Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#pre…> +``` diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 2f32b85..8dbb067 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -1141,4 +1141,8 @@ ## References: -* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-2022050… +```{toctree} +:maxdepth: 1 + +AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-w…> +``` diff --git a/Documentation/arch/index.md b/Documentation/arch/index.md index a0f1050..adf00fb 100644 --- a/Documentation/arch/index.md +++ b/Documentation/arch/index.md @@ -5,7 +5,15 @@ ## RISC-V -- [RISC-V documentation](riscv/index.md) +```{toctree} +:maxdepth: 1 + +RISC-V documentation <riscv/index.md> +``` ## x86 -- [x86 documentation](x86/index.md) +```{toctree} +:maxdepth: 1 + +x86 documentation <x86/index.md> +``` diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index c7115b4..3ddff51 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -2,7 +2,11 @@ This section contains documentation about coreboot on x86 architecture. -* [x86 PAE support](pae.md) +```{toctree} +:maxdepth: 1 + +x86 PAE support <pae.md> +``` ## State of x86_64 support At the moment there's only experimental x86_64 support. @@ -43,8 +47,12 @@ ## Reference implementation The reference implementation is -* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md) -* [QEMU Q35](../../mainboard/emulation/qemu-q35.md) +```{toctree} +:maxdepth: 1 + +QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md> +QEMU Q35 <../../mainboard/emulation/qemu-q35.md> +``` ## TODO * Identity map memory above 4GiB in ramstage diff --git a/Documentation/community/index.md b/Documentation/community/index.md index 1363eb0..92bf6e5 100644 --- a/Documentation/community/index.md +++ b/Documentation/community/index.md @@ -1,6 +1,10 @@ # Community -* [Code of Conduct](code_of_conduct.md) -* [Language style](language_style.md) -* [Community forums](forums.md) -* [coreboot at conferences](conferences.md) +```{toctree} +:maxdepth: 1 + +Code of Conduct <code_of_conduct.md> +Language style <language_style.md> +Community forums <forums.md> +coreboot at conferences <conferences.md> +``` diff --git a/Documentation/conf.py b/Documentation/conf.py index 143e60d..b0f2975 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -1,46 +1,34 @@ -# -*- coding: utf-8 -*- -import subprocess -from recommonmark.parser import CommonMarkParser -import sphinx - -# Get Sphinx version -major = 0 -minor = 0 -patchlevel = 0 -version = sphinx.__version__.split(".") -if len(version) > 1: - major = int(version[0]) - minor = int(version[1]) - if len(version) > 2: - patchlevel = int(version[2]) - -# Add any paths that contain templates here, relative to this directory. -templates_path = ['_templates'] - -# The suffix(es) of source filenames. -source_suffix = ['.md'] - -# The master toctree document. -master_doc = 'index' - -# General information about the project. -project = u'coreboot' -copyright = u'CC-by 4.0 the coreboot project' -author = u'the coreboot project' - -# The version info for the project you're documenting, acts as replacement for -# |version| and |release|, also used in various other places throughout the -# built documents. +# Configuration file for the Sphinx documentation builder. # -# The full version, including alpha/beta/rc tags. +# For the full list of built-in configuration values, see the documentation: +# https://www.sphinx-doc.org/en/master/usage/configuration.html + +# -- Project information ----------------------------------------------------- +# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-infor… + +import subprocess + +project = 'coreboot' +copyright = 'CC-by 4.0 the coreboot project' +author = 'the coreboot project' + release = subprocess.check_output(('git', 'describe')).decode("utf-8") # The short X.Y version. version = release.split("-")[0] -extensions = [] -# Load recommonmark, supported since 1.8+ -if major >= 2 or (major == 1 and minor >= 8): - extensions += ['recommonmark'] + +# -- General configuration --------------------------------------------------- +# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-confi… + +extensions = ["myst_parser"] + +myst_heading_anchors = 5 + +templates_path = ['_templates'] +exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' # Try to load DITAA try: @@ -57,62 +45,11 @@ # Usually you set "language" from the command line for these cases. language = 'en' -# List of patterns, relative to source directory, that match files and -# directories to ignore when looking for source files. -# This patterns also effect to html_static_path and html_extra_path -exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] +# -- Options for HTML output ------------------------------------------------- +# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-h… -# The name of the Pygments (syntax highlighting) style to use. -pygments_style = 'sphinx' - -# A list of ignored prefixes for module index sorting. -# modindex_common_prefix = [] - -# If true, keep warnings as "system message" paragraphs in the built documents. -# keep_warnings = False - -# If true, `todo` and `todoList` produce output, else they produce nothing. -todo_include_todos = False - - -# -- Options for HTML output ---------------------------------------------- - -# The theme to use for HTML and HTML Help pages. See the documentation for -# a list of builtin themes. -# html_theme = 'sphinx_rtd_theme' - -# Add any paths that contain custom static files (such as style sheets) here, -# relative to this directory. They are copied after the builtin static files, -# so a file named "default.css" will overwrite the builtin "default.css". html_static_path = ['_static'] - html_css_files = [ 'theme_overrides.css', # override wide tables in RTD theme ] - -# Output file base name for HTML help builder. -htmlhelp_basename = 'corebootdoc' - -enable_auto_toc_tree = True - -class MyCommonMarkParser(CommonMarkParser): - # remove this hack once upstream RecommonMark supports inline code - def visit_code(self, mdnode): - from docutils import nodes - n = nodes.literal(mdnode.literal, mdnode.literal) - self.current_node.append(n) - -def setup(app): - from recommonmark.transform import AutoStructify - # Load recommonmark on old Sphinx - if major == 1 and minor < 8: - app.add_source_parser('.md', MyCommonMarkParser) - - app.add_config_value('recommonmark_config', { - 'enable_auto_toc_tree': True, - 'enable_auto_doc_ref': False, # broken in Sphinx 1.6+ - 'enable_eval_rst': True, - 'url_resolver': lambda url: '/' + url - }, True) - app.add_transform(AutoStructify) diff --git a/Documentation/contributing/index.md b/Documentation/contributing/index.md index 61a8ca6..38a67c0 100644 --- a/Documentation/contributing/index.md +++ b/Documentation/contributing/index.md @@ -1,7 +1,11 @@ # Contributing -* [Coding Style](coding_style.md) -* [Gerrit Guidelines](gerrit_guidelines.md) -* [Project Ideas](project_ideas.md) -* [Documentation Ideas](documentation_ideas.md) -* [Google Summer of Code](gsoc.md) +```{toctree} +:maxdepth: 1 + +Coding Style <coding_style.md> +Gerrit Guidelines <gerrit_guidelines.md> +Project Ideas <project_ideas.md> +Documentation Ideas <documentation_ideas.md> +Google Summer of Code <gsoc.md> +``` diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 95c1e31..9b7d25c 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -8,10 +8,14 @@ Some of the drivers currently available include: -* [Intel DPTF](dptf.md) -* [IPMI KCS](ipmi_kcs.md) -* [SMMSTORE](smmstore.md) -* [SMMSTOREv2](smmstorev2.md) -* [SoundWire](soundwire.md) -* [USB4 Retimer](retimer.md) -* [CBFS SMBIOS hooks](cbfs_smbios.md) +```{toctree} +:maxdepth: 1 + +Intel DPTF <dptf.md> +IPMI KCS <ipmi_kcs.md> +SMMSTORE <smmstore.md> +SMMSTOREv2 <smmstorev2.md> +SoundWire <soundwire.md> +USB4 Retimer <retimer.md> +CBFS SMBIOS hooks <cbfs_smbios.md> +``` diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md index 7082747..d68e51c 100644 --- a/Documentation/drivers/smmstore.md +++ b/Documentation/drivers/smmstore.md @@ -128,7 +128,11 @@ ## External links -* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… +```{toctree} +:maxdepth: 1 + +A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_…> +``` Note, this differs significantly from coreboot's implementation. [SMM]: ../security/smm.md diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 70aa60d..03d3c7c 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -215,7 +215,11 @@ ## External links -* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… +```{toctree} +:maxdepth: 1 + +A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_…> +``` Note that this differs significantly from coreboot's implementation. [SMM]: ../security/smm.md diff --git a/Documentation/external_docs.md b/Documentation/external_docs.md index b5ee908..47c7600 100644 --- a/Documentation/external_docs.md +++ b/Documentation/external_docs.md @@ -17,13 +17,21 @@ * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-in… * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-in… * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_bu… -* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html) +```{toctree} +:maxdepth: 1 + +Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html> +``` ## General Information -* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page) -* [Interface BUS](http://www.interfacebus.com/) +```{toctree} +:maxdepth: 1 + +OS Dev <https://wiki.osdev.org/Categorized_Main_Page> +Interface BUS <http://www.interfacebus.com/> +``` ## OpenSecurityTraining2 @@ -43,10 +51,14 @@ Below is a list of currently available courses that can help understand the inner workings of coreboot and other firmware-related topics: -* [coreboot design principles and boot process](https://ost2.fyi/Arch4031) -* [x86-64 Assembly](https://ost2.fyi/Arch1001) -* [x86-64 OS Internals](https://ost2.fyi/Arch2001) -* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001) +```{toctree} +:maxdepth: 1 + +coreboot design principles and boot process <https://ost2.fyi/Arch4031> +x86-64 Assembly <https://ost2.fyi/Arch1001> +x86-64 OS Internals <https://ost2.fyi/Arch2001> +x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001> +``` There are [additional security courses](https://p.ost2.fyi/courses) at the site as well (such as @@ -54,47 +66,79 @@ ## Firmware Specifications & Information -* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios) -* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash) -* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboard… +```{toctree} +:maxdepth: 1 + +System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios> +Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash> +PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desk…> +``` ### ACPI -* [ACPI Specs](https://uefi.org/acpi/specs) -* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf) -* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/L… -* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_… +```{toctree} +:maxdepth: 1 + +ACPI Specs <https://uefi.org/acpi/specs> +ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf> +ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-…> +ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_L…> +``` ### Security -* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard) +```{toctree} +:maxdepth: 1 + +Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secur…> +``` ## Hardware information -* [WikiChip](https://en.wikichip.org/wiki/WikiChip) -* [Sandpile](https://www.sandpile.org/) -* [CPU-World](https://www.cpu-world.com/index.html) -* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html) +```{toctree} +:maxdepth: 1 + +WikiChip <https://en.wikichip.org/wiki/WikiChip> +Sandpile <https://www.sandpile.org/> +CPU-World <https://www.cpu-world.com/index.html> +CPU-Upgrade <https://www.cpu-upgrade.com/index.html> +``` ### Hardware Specifications & Standards * [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG -* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) +```{toctree} +:maxdepth: 1 + +eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> +``` * [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel * [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/e…, [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP * [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP -* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED) -* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) +```{toctree} +:maxdepth: 1 + +I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED> +Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> +``` * [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications * [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/l… - Intel -* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED) +```{toctree} +:maxdepth: 1 + +PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED> +``` * [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum -* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED) +```{toctree} +:maxdepth: 1 + +SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED> +``` * [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum * [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum * [USB](https://www.usb.org/documents) - USB Implementers Forum @@ -133,5 +177,9 @@ ## Infrastructure software -* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.htm… -* [GNU Make](https://www.gnu.org/software/make/manual/) +```{toctree} +:maxdepth: 1 + +Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html> +GNU Make <https://www.gnu.org/software/make/manual/> +``` diff --git a/Documentation/getting_started/build_system.md b/Documentation/getting_started/build_system.md index 35ed187..4c91f43 100644 --- a/Documentation/getting_started/build_system.md +++ b/Documentation/getting_started/build_system.md @@ -75,7 +75,7 @@ Note that the second line must start with a tab, not spaces. -```eval_rst +```{eval-rst} See also :doc:`../tutorial/managing_local_additions`. ``` diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index fd0267a..4baaa7a 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -167,7 +167,7 @@ As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register supports four different types of GPIO reset as: -```eval_rst +```{eval-rst} +------------------------+----------------+-------------+-------------+ | | | PAD Reset ? | + PAD Reset Config + Platform Reset +-------------+-------------+ diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 01dbe8c..7180c96 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -1,10 +1,14 @@ # Getting Started -* [coreboot architecture](architecture.md) -* [Build System](build_system.md) -* [Submodules](submodules.md) -* [Kconfig](kconfig.md) -* [Writing Documentation](writing_documentation.md) -* [Setting up GPIOs](gpio.md) -* [Adding devices to a device tree](devicetree.md) -* [Frequently Asked Questions](faq.md) +```{toctree} +:maxdepth: 1 + +coreboot architecture <architecture.md> +Build System <build_system.md> +Submodules <submodules.md> +Kconfig <kconfig.md> +Writing Documentation <writing_documentation.md> +Setting up GPIOs <gpio.md> +Adding devices to a device tree <devicetree.md> +Frequently Asked Questions <faq.md> +``` diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index ddd3276..c9e9b3c 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -11,8 +11,12 @@ The official Kconfig source and documentation is kept at kernel.org: -- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tre… -- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-lang… +```{toctree} +:maxdepth: 1 + +Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/script…> +Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt> +``` The advantage to using Kconfig is that it allows users to easily select the high level features of the project to be enabled or disabled at build time. diff --git a/Documentation/gfx/display-panel.md b/Documentation/gfx/display-panel.md index 3bab089..8cd5902 100644 --- a/Documentation/gfx/display-panel.md +++ b/Documentation/gfx/display-panel.md @@ -22,7 +22,7 @@ referenced in Intel's respective registers listing. You need the values for `PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`: -```eval_rst +```{eval-rst} +-----------------------------+---------------------------------------+-----+ | Intel docs | devicetree.cb | eDP | +-----------------------------+---------------------------------------+-----+ diff --git a/Documentation/index.md b/Documentation/index.md index 6d91aa0..d205151 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -170,34 +170,38 @@ Contents: -* [Getting Started](getting_started/index.md) -* [Tutorial](tutorial/index.md) -* [Contributing](contributing/index.md) -* [Community](community/index.md) -* [Payloads](payloads.md) -* [Distributions](distributions.md) -* [Technotes](technotes/index.md) -* [ACPI](acpi/index.md) -* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) -* [Display panel](gfx/display-panel.md) -* [CPU Architecture](arch/index.md) -* [Platform independent drivers](drivers/index.md) -* [Northbridge](northbridge/index.md) -* [System on Chip](soc/index.md) -* [Mainboard](mainboard/index.md) -* [Payloads](lib/payloads/index.md) -* [Libraries](lib/index.md) -* [Options](lib/option.md) -* [Security](security/index.md) -* [SuperIO](superio/index.md) -* [Vendorcode](vendorcode/index.md) -* [Utilities](util.md) -* [Software Bill of Materials](sbom/sbom.md) -* [Project infrastructure & services](infrastructure/index.md) -* [Boards supported in each release directory](releases/boards_supported_on_branches.md) -* [Release notes](releases/index.md) -* [Acronyms & Definitions](acronyms.md) -* [External Resources](external_docs.md) -* [Documentation License](documentation_license.md) +```{toctree} +:maxdepth: 1 + +Getting Started <getting_started/index.md> +Tutorial <tutorial/index.md> +Contributing <contributing/index.md> +Community <community/index.md> +Payloads <payloads.md> +Distributions <distributions.md> +Technotes <technotes/index.md> +ACPI <acpi/index.md> +Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md> +Display panel <gfx/display-panel.md> +CPU Architecture <arch/index.md> +Platform independent drivers <drivers/index.md> +Northbridge <northbridge/index.md> +System on Chip <soc/index.md> +Mainboard <mainboard/index.md> +Payloads <lib/payloads/index.md> +Libraries <lib/index.md> +Options <lib/option.md> +Security <security/index.md> +SuperIO <superio/index.md> +Vendorcode <vendorcode/index.md> +Utilities <util.md> +Software Bill of Materials <sbom/sbom.md> +Project infrastructure & services <infrastructure/index.md> +Boards supported in each release directory <releases/boards_supported_on_branches.md> +Release notes <releases/index.md> +Acronyms & Definitions <acronyms.md> +External Resources <external_docs.md> +Documentation License <documentation_license.md> +``` [Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Docu… diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md index b200140e..dc4216d 100644 --- a/Documentation/infrastructure/builders.md +++ b/Documentation/infrastructure/builders.md @@ -93,11 +93,19 @@ Most of the time on the builders is taken up by the coreboot main and coreboot gerrit builds. -* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +```{toctree} +:maxdepth: 1 + +coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/> +``` ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) -* [coreboot main build](https://qa.coreboot.org/job/coreboot/) +```{toctree} +:maxdepth: 1 + +coreboot main build <https://qa.coreboot.org/job/coreboot/> +``` ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md index 6748637..75ad61b 100644 --- a/Documentation/infrastructure/index.md +++ b/Documentation/infrastructure/index.md @@ -4,9 +4,17 @@ ## Services -* [Project services](services.md) -* [Administrator's handbook](admin.md) +```{toctree} +:maxdepth: 1 + +Project services <services.md> +Administrator's handbook <admin.md> +``` ## Jenkins builders and builds -* [Setting up Jenkins build machines](builders.md) -* [Coverity Scan integration](coverity.md) +```{toctree} +:maxdepth: 1 + +Setting up Jenkins build machines <builders.md> +Coverity Scan integration <coverity.md> +``` diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index d64b4e9..612b883 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -3,7 +3,11 @@ This section contains documentation about coreboot internal technical information and libraries. -- [Flashmap and Flashmap Descriptor](flashmap.md) -- [ABI data consumption](abi-data-consumption.md) -- [Timestamps](timestamp.md) -- [Firmware Configuration Interface](fw_config.md) +```{toctree} +:maxdepth: 1 + +Flashmap and Flashmap Descriptor <flashmap.md> +ABI data consumption <abi-data-consumption.md> +Timestamps <timestamp.md> +Firmware Configuration Interface <fw_config.md> +``` diff --git a/Documentation/lib/payloads/index.md b/Documentation/lib/payloads/index.md index 44daef1..f9f00b6 100644 --- a/Documentation/lib/payloads/index.md +++ b/Documentation/lib/payloads/index.md @@ -8,4 +8,8 @@ ## FIT -- [uImage.FIT support](fit.md) +```{toctree} +:maxdepth: 1 + +uImage.FIT support <fit.md> +``` diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md index 07d23c6..79aa8ff 100644 --- a/Documentation/mainboard/acer/g43t-am3.md +++ b/Documentation/mainboard/acer/g43t-am3.md @@ -5,7 +5,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | Intel G43 (called x4x in coreboot code) | +------------------+--------------------------------------------------+ @@ -69,7 +69,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +-------------------+---------------------+ | Type | Value | +===================+=====================+ @@ -122,7 +122,7 @@ -w coreboot.rom ``` -```eval_rst +```{eval-rst} In addition to the information here, please see the :doc:`../../tutorial/flashing_firmware/index`. ``` diff --git a/Documentation/mainboard/amd/pademelon/pademelon.md b/Documentation/mainboard/amd/pademelon/pademelon.md index 5f053d4..22dd7e2 100644 --- a/Documentation/mainboard/amd/pademelon/pademelon.md +++ b/Documentation/mainboard/amd/pademelon/pademelon.md @@ -33,7 +33,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------+ | Type | Value | +=====================+====================+ @@ -53,7 +53,7 @@ ## Technology -```eval_rst +```{eval-rst} +---------------+------------------------------+ | Fan control | Using fintek F81803A | +---------------+------------------------------+ @@ -63,7 +63,7 @@ ## Description of pictures within this document -```eval_rst +```{eval-rst} +----------------------------+----------------------------------------+ |pademelon.jpg | Motherboard with components identified | +----------------------------+----------------------------------------+ diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index a4f6e57..b3c484e 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -11,7 +11,7 @@ FSP Information: -```eval_rst +```{eval-rst} +-----------------------------+-------------------+-------------------+ | FSP Project Name | Directory | Specification | +-----------------------------+-------------------+-------------------+ @@ -114,7 +114,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Skylake/Kaby Lake (LGA1151) | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asrock/h77pro4-m.md b/Documentation/mainboard/asrock/h77pro4-m.md index 81fb000..5ad4479 100644 --- a/Documentation/mainboard/asrock/h77pro4-m.md +++ b/Documentation/mainboard/asrock/h77pro4-m.md @@ -5,7 +5,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ @@ -71,7 +71,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -115,7 +115,7 @@ The use of `--noverify-all` is required since the Management Engine region is not readable even by the host. -```eval_rst +```{eval-rst} In addition to the information here, please see the :doc:`../../tutorial/flashing_firmware/index`. ``` diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 9d5c288..5cbaa7f 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -4,7 +4,7 @@ ## Required proprietary blobs -```eval_rst +```{eval-rst} Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. ``` @@ -75,7 +75,7 @@ in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. -```eval_rst +```{eval-rst} Please also see :doc:`../../northbridge/intel/haswell/known-issues`. ``` @@ -111,7 +111,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/haswell/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md index 7761531..dbfb99c 100644 --- a/Documentation/mainboard/asus/a88xm-e.md +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -14,7 +14,7 @@ A10 Richland is recommended for the best performance and working IOMMU. -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | A88XM-E | | +------------------+--------------------------------------------------+ @@ -36,7 +36,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md index ce7c2497..790a2f7 100644 --- a/Documentation/mainboard/asus/f2a85-m.md +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -15,7 +15,7 @@ the CPU architecture in these CPUs/APUs is [Piledriver], and their GPU is [TeraScale 3] (VLIW4-based). -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | F2A85-M | | +------------------+--------------------------------------------------+ @@ -35,7 +35,7 @@ +------------------+--------------------------------------------------+ ``` -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | F2A85-M LE | | +------------------+--------------------------------------------------+ @@ -55,7 +55,7 @@ +------------------+--------------------------------------------------+ ``` -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | F2A85-M PRO | | +------------------+--------------------------------------------------+ @@ -77,7 +77,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/asus/p2b-ls.md b/Documentation/mainboard/asus/p2b-ls.md index c119993..c1bb1c4b 100644 --- a/Documentation/mainboard/asus/p2b-ls.md +++ b/Documentation/mainboard/asus/p2b-ls.md @@ -10,7 +10,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------------+ | Type | Value | +=====================+===========================+ @@ -90,7 +90,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | Intel I440BX | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p3b-f.md b/Documentation/mainboard/asus/p3b-f.md index 3db2097..addc7d9 100644 --- a/Documentation/mainboard/asus/p3b-f.md +++ b/Documentation/mainboard/asus/p3b-f.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------------+ | Type | Value | +=====================+===========================+ @@ -88,7 +88,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | Intel I440BX | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p5q.md b/Documentation/mainboard/asus/p5q.md index ec20887..0b5fcb6 100644 --- a/Documentation/mainboard/asus/p5q.md +++ b/Documentation/mainboard/asus/p5q.md @@ -32,7 +32,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +-------------------+----------------+ | Type | Value | +===================+================+ @@ -56,7 +56,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+---------------------------------------------------+ | Northbridge | Intel P45 (called x4x in coreboot code) | +------------------+---------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8c_ws.md b/Documentation/mainboard/asus/p8c_ws.md index a9aa589..63f80ac 100644 --- a/Documentation/mainboard/asus/p8c_ws.md +++ b/Documentation/mainboard/asus/p8c_ws.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -69,7 +69,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index a4b54cd..cc0dfb1 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -84,7 +84,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md index 713c794..3f9bf36 100644 --- a/Documentation/mainboard/asus/p8h61-m_pro.md +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -78,7 +78,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8h77-v.md b/Documentation/mainboard/asus/p8h77-v.md index 97b84ea..7aec6c3 100644 --- a/Documentation/mainboard/asus/p8h77-v.md +++ b/Documentation/mainboard/asus/p8h77-v.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -56,7 +56,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8z77-m.md b/Documentation/mainboard/asus/p8z77-m.md index a701169..23b28ee 100644 --- a/Documentation/mainboard/asus/p8z77-m.md +++ b/Documentation/mainboard/asus/p8z77-m.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -112,7 +112,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md index 8bfac25..93400bc 100644 --- a/Documentation/mainboard/asus/p8z77-m_pro.md +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -143,7 +143,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md index dba02b9..e6ae9a8 100644 --- a/Documentation/mainboard/asus/p8z77-v.md +++ b/Documentation/mainboard/asus/p8z77-v.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -86,7 +86,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/asus/wifigo_v1.md b/Documentation/mainboard/asus/wifigo_v1.md index d5ad327..1685c68 100644 --- a/Documentation/mainboard/asus/wifigo_v1.md +++ b/Documentation/mainboard/asus/wifigo_v1.md @@ -8,7 +8,7 @@ I managed to grope the most pinout of the proprietary connector. See [Mini PCIe pinout] for more info. -```eval_rst +```{eval-rst} +------------+----------+-----------+------------+----------+-----------+ | WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin | +============+==========+===========+============+==========+===========+ diff --git a/Documentation/mainboard/cavium/cn8100_sff_evb.md b/Documentation/mainboard/cavium/cn8100_sff_evb.md index b16a8ae..4498ca3 100644 --- a/Documentation/mainboard/cavium/cn8100_sff_evb.md +++ b/Documentation/mainboard/cavium/cn8100_sff_evb.md @@ -17,7 +17,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -58,7 +58,7 @@ ## Technology -```eval_rst +```{eval-rst} +---------------+----------------------------------------+ | SoC | :doc:`../../soc/cavium/cn81xx/index` | +---------------+----------------------------------------+ diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md index 3267561..d67ca81 100644 --- a/Documentation/mainboard/clevo/n130wu/index.md +++ b/Documentation/mainboard/clevo/n130wu/index.md @@ -2,7 +2,7 @@ ## Hardware ### Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------+ | CPU | Intel i7-8550U | +------------------+--------------------------------+ @@ -15,7 +15,7 @@ ``` ### Flash chip -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/dell/optiplex_9010.md b/Documentation/mainboard/dell/optiplex_9010.md index f22623d..3168591 100644 --- a/Documentation/mainboard/dell/optiplex_9010.md +++ b/Documentation/mainboard/dell/optiplex_9010.md @@ -6,7 +6,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------+---------------------------------------------------------------+ | CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) | +------------+---------------------------------------------------------------+ @@ -28,7 +28,7 @@ ## Required proprietary blobs -```eval_rst +```{eval-rst} +------------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +==================+=================================+=====================+ @@ -50,7 +50,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------------+ | Type | Value | +=====================+==========================+ diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md index 1c72d6c..0fa3db3 100644 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -63,7 +63,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | SoC | Intel Atom Processor N3710 | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index 9010709..da72e48 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -14,7 +14,7 @@ FSP Information: -```eval_rst +```{eval-rst} +-----------------------------+-------------------+-------------------+ | FSP Project Name | Directory | Specification | +-----------------------------+-------------------+-------------------+ @@ -116,7 +116,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | SoC | Intel Kaby Lake U | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/foxconn/d41s.md b/Documentation/mainboard/foxconn/d41s.md index fe14057..45a86d4 100644 --- a/Documentation/mainboard/foxconn/d41s.md +++ b/Documentation/mainboard/foxconn/d41s.md @@ -14,7 +14,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------+ | Type | Value | +=====================+========+ @@ -56,7 +56,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+------------------+ | Northbridge | Intel Pinevew | +------------------+------------------+ diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l.md b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md index 57c4945..b42cd81 100644 --- a/Documentation/mainboard/gigabyte/ga-g41m-es2l.md +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md @@ -6,7 +6,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Type | Value | +==================+==================================================+ @@ -30,7 +30,7 @@ ## Preparation -```eval_rst +```{eval-rst} For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`. ``` @@ -140,7 +140,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} In addition to the information here, please see the :doc:`../../tutorial/flashing_firmware/index`. ``` diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md index 0632585..824026f 100644 --- a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md +++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md @@ -5,7 +5,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -59,7 +59,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/2170p.md b/Documentation/mainboard/hp/2170p.md index 5f67c38..6b8060e 100644 --- a/Documentation/mainboard/hp/2170p.md +++ b/Documentation/mainboard/hp/2170p.md @@ -74,7 +74,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Sandy/Ivy Bridge (FCPGA988) | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/2560p.md b/Documentation/mainboard/hp/2560p.md index 65a87d1..4565171 100644 --- a/Documentation/mainboard/hp/2560p.md +++ b/Documentation/mainboard/hp/2560p.md @@ -80,7 +80,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Sandy/Ivy Bridge (FCPGA988) | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md index 857a1d9..9646ba9 100644 --- a/Documentation/mainboard/hp/8760w.md +++ b/Documentation/mainboard/hp/8760w.md @@ -7,7 +7,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -66,7 +66,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md index 72df9e3..f078397 100644 --- a/Documentation/mainboard/hp/compaq_8200_sff.md +++ b/Documentation/mainboard/hp/compaq_8200_sff.md @@ -13,7 +13,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-------------------------+ | Type | Value | +=====================+=========================+ @@ -128,7 +128,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/compaq_8300_usdt.md b/Documentation/mainboard/hp/compaq_8300_usdt.md index c2800b3..4c2989a 100644 --- a/Documentation/mainboard/hp/compaq_8300_usdt.md +++ b/Documentation/mainboard/hp/compaq_8300_usdt.md @@ -5,7 +5,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-------------+ | Type | Value | +=====================+=============+ @@ -42,7 +42,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md index 5d35c30..6fafbe1 100644 --- a/Documentation/mainboard/hp/elitebook_820_g2.md +++ b/Documentation/mainboard/hp/elitebook_820_g2.md @@ -124,7 +124,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+-----------------------------+ | SoC | Intel Broadwell | +------------------+-----------------------------+ diff --git a/Documentation/mainboard/hp/folio_9480m.md b/Documentation/mainboard/hp/folio_9480m.md index 0fededf..912bf93 100644 --- a/Documentation/mainboard/hp/folio_9480m.md +++ b/Documentation/mainboard/hp/folio_9480m.md @@ -138,7 +138,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+-----------------------------+ | CPU | Intel Haswell-ULT | +------------------+-----------------------------+ diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md index 1167620..303b59a 100644 --- a/Documentation/mainboard/hp/z220_sff.md +++ b/Documentation/mainboard/hp/z220_sff.md @@ -13,7 +13,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-------------+ | Type | Value | +=====================+=============+ @@ -58,7 +58,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 519d888..6178738 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -4,240 +4,392 @@ ## 51NB -- [X210](51nb/x210.md) +```{toctree} +:maxdepth: 1 + +X210 <51nb/x210.md> +``` ## Acer -- [G43T-AM3](acer/g43t-am3.md) +```{toctree} +:maxdepth: 1 + +G43T-AM3 <acer/g43t-am3.md> +``` ## AMD -- [pademelon](amd/pademelon/pademelon.md) +```{toctree} +:maxdepth: 1 + +pademelon <amd/pademelon/pademelon.md> +``` ## ASRock -- [H77 Pro4-M](asrock/h77pro4-m.md) -- [H81M-HDS](asrock/h81m-hds.md) -- [H110M-DVS](asrock/h110m-dvs.md) +```{toctree} +:maxdepth: 1 + +H77 Pro4-M <asrock/h77pro4-m.md> +H81M-HDS <asrock/h81m-hds.md> +H110M-DVS <asrock/h110m-dvs.md> +``` ## ASUS -- [A88XM-E](asus/a88xm-e.md) -- [F2A85-M](asus/f2a85-m.md) -- [P2B-LS](asus/p2b-ls.md) -- [P3B-F](asus/p3b-f.md) -- [P5Q](asus/p5q.md) -- [P8C WS](asus/p8c_ws.md) -- [P8H61-M LX](asus/p8h61-m_lx.md) -- [P8H61-M Pro](asus/p8h61-m_pro.md) -- [P8H77-V](asus/p8h77-v.md) -- [P8Z77-M](asus/p8z77-m.md) -- [P8Z77-M Pro](asus/p8z77-m_pro.md) -- [P8Z77-V](asus/p8z77-v.md) -- [wifigo_v1](asus/wifigo_v1.md) +```{toctree} +:maxdepth: 1 + +A88XM-E <asus/a88xm-e.md> +F2A85-M <asus/f2a85-m.md> +P2B-LS <asus/p2b-ls.md> +P3B-F <asus/p3b-f.md> +P5Q <asus/p5q.md> +P8C WS <asus/p8c_ws.md> +P8H61-M LX <asus/p8h61-m_lx.md> +P8H61-M Pro <asus/p8h61-m_pro.md> +P8H77-V <asus/p8h77-v.md> +P8Z77-M <asus/p8z77-m.md> +P8Z77-M Pro <asus/p8z77-m_pro.md> +P8Z77-V <asus/p8z77-v.md> +wifigo_v1 <asus/wifigo_v1.md> +``` ## Cavium -- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +```{toctree} +:maxdepth: 1 + +CN81XX EVB SFF <cavium/cn8100_sff_evb.md> +``` ## Clevo -- [N130WU / N131WU](clevo/n130wu/index.md) +```{toctree} +:maxdepth: 1 + +N130WU / N131WU <clevo/n130wu/index.md> +``` ## Dell -- [OptiPlex 9010 SFF](dell/optiplex_9010.md) +```{toctree} +:maxdepth: 1 + +OptiPlex 9010 SFF <dell/optiplex_9010.md> +``` ## Emulation The boards in this section are not real mainboards, but emulators. -- [Spike RISC-V emulator](emulation/spike-riscv.md) -- [QEMU RISC-V emulator](emulation/qemu-riscv.md) -- [QEMU AArch64 emulator](emulation/qemu-aarch64.md) -- [QEMU x86 Q35](emulation/qemu-q35.md) -- [QEMU x86 PC](emulation/qemu-i440fx.md) -- [QEMU POWER9](emulation/qemu-power9.md) +```{toctree} +:maxdepth: 1 + +Spike RISC-V emulator <emulation/spike-riscv.md> +QEMU RISC-V emulator <emulation/qemu-riscv.md> +QEMU AArch64 emulator <emulation/qemu-aarch64.md> +QEMU x86 Q35 <emulation/qemu-q35.md> +QEMU x86 PC <emulation/qemu-i440fx.md> +QEMU POWER9 <emulation/qemu-power9.md> +``` ## Facebook -- [FBG-1701](facebook/fbg1701.md) -- [Monolith](facebook/monolith.md) +```{toctree} +:maxdepth: 1 + +FBG-1701 <facebook/fbg1701.md> +Monolith <facebook/monolith.md> +``` ## Foxconn -- [D41S](foxconn/d41s.md) +```{toctree} +:maxdepth: 1 + +D41S <foxconn/d41s.md> +``` ## Gigabyte -- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md) -- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) +```{toctree} +:maxdepth: 1 + +GA-G41M-ES2L <gigabyte/ga-g41m-es2l.md> +GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md> +``` ## HP -- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) -- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md) -- [Z220 Workstation SFF](hp/z220_sff.md) +```{toctree} +:maxdepth: 1 + +Compaq 8200 Elite SFF <hp/compaq_8200_sff.md> +Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md> +Z220 Workstation SFF <hp/z220_sff.md> +``` ### EliteBook series -- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) -- [HP Sure Start](hp/hp_sure_start.md) -- [EliteBook 2170p](hp/2170p.md) -- [EliteBook 2560p](hp/2560p.md) -- [EliteBook 8760w](hp/8760w.md) -- [EliteBook Folio 9480m](hp/folio_9480m.md) -- [EliteBook 820 G2](hp/elitebook_820_g2.md) +```{toctree} +:maxdepth: 1 + +HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md> +HP Sure Start <hp/hp_sure_start.md> +EliteBook 2170p <hp/2170p.md> +EliteBook 2560p <hp/2560p.md> +EliteBook 8760w <hp/8760w.md> +EliteBook Folio 9480m <hp/folio_9480m.md> +EliteBook 820 G2 <hp/elitebook_820_g2.md> +``` ## Intel -- [DG43GT](intel/dg43gt.md) -- [DQ67SW](intel/dq67sw.md) -- [KBLRVP11](intel/kblrvp11.md) +```{toctree} +:maxdepth: 1 + +DG43GT <intel/dg43gt.md> +DQ67SW <intel/dq67sw.md> +KBLRVP11 <intel/kblrvp11.md> +``` ## Kontron -- [mAL-10](kontron/mal10.md) +```{toctree} +:maxdepth: 1 + +mAL-10 <kontron/mal10.md> +``` ## Lenovo -- [Mainboard codenames](lenovo/codenames.md) -- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) -- [R60](lenovo/r60.md) -- [T4xx common](lenovo/t4xx_series.md) -- [X2xx common](lenovo/x2xx_series.md) -- [vboot](lenovo/vboot.md) +```{toctree} +:maxdepth: 1 + +Mainboard codenames <lenovo/codenames.md> +Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md> +R60 <lenovo/r60.md> +T4xx common <lenovo/t4xx_series.md> +X2xx common <lenovo/x2xx_series.md> +vboot <lenovo/vboot.md> +``` ### GM45 series -- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md) -- [X301](lenovo/x301.md) +```{toctree} +:maxdepth: 1 + +X200 / T400 / T500 / X301 common <lenovo/montevina_series.md> +X301 <lenovo/x301.md> +``` ### Arrandale series -- [T410](lenovo/t410.md) +```{toctree} +:maxdepth: 1 + +T410 <lenovo/t410.md> +``` ### Sandy Bridge series -- [T420](lenovo/t420.md) -- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) -- [X1](lenovo/x1.md) +```{toctree} +:maxdepth: 1 + +T420 <lenovo/t420.md> +T420 / T520 / X220 / T420s / W520 common <lenovo/Sandy_Bridge_series.md> +X1 <lenovo/x1.md> +``` ### Ivy Bridge series -- [T430](lenovo/t430.md) -- [T530 / W530](lenovo/w530.md) -- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) -- [T431s](lenovo/t431s.md) -- [X230s](lenovo/x230s.md) -- [Internal flashing](lenovo/ivb_internal_flashing.md) +```{toctree} +:maxdepth: 1 + +T430 <lenovo/t430.md> +T530 / W530 <lenovo/w530.md> +T430 / T530 / X230 / W530 common <lenovo/Ivy_Bridge_series.md> +T431s <lenovo/t431s.md> +X230s <lenovo/x230s.md> +Internal flashing <lenovo/ivb_internal_flashing.md> +``` ### Haswell series -- [T440p](lenovo/t440p.md) +```{toctree} +:maxdepth: 1 + +T440p <lenovo/t440p.md> +``` ## Libretrend -- [LT1000](libretrend/lt1000.md) +```{toctree} +:maxdepth: 1 + +LT1000 <libretrend/lt1000.md> +``` ## MSI -- [MS-7707](msi/ms7707/ms7707.md) +```{toctree} +:maxdepth: 1 + +MS-7707 <msi/ms7707/ms7707.md> +``` ## OCP -- [Delta Lake](ocp/deltalake.md) -- [Tioga Pass](ocp/tiogapass.md) +```{toctree} +:maxdepth: 1 + +Delta Lake <ocp/deltalake.md> +Tioga Pass <ocp/tiogapass.md> +``` ## Open Cellular -- [Elgon](opencellular/elgon.md) +```{toctree} +:maxdepth: 1 + +Elgon <opencellular/elgon.md> +``` ## PC Engines -- [APU1](pcengines/apu1.md) -- [APU2](pcengines/apu2.md) +```{toctree} +:maxdepth: 1 + +APU1 <pcengines/apu1.md> +APU2 <pcengines/apu2.md> +``` ## Portwell -- [PQ7-M107](portwell/pq7-m107.md) +```{toctree} +:maxdepth: 1 + +PQ7-M107 <portwell/pq7-m107.md> +``` ## Prodrive -- [Hermes](prodrive/hermes.md) +```{toctree} +:maxdepth: 1 + +Hermes <prodrive/hermes.md> +``` ## Purism -- [Librem 14](purism/librem_14.md) -- [Librem Mini](purism/librem_mini.md) +```{toctree} +:maxdepth: 1 + +Librem 14 <purism/librem_14.md> +Librem Mini <purism/librem_mini.md> +``` ## Protectli -- [FW2B / FW4B](protectli/fw2b_fw4b.md) -- [FW6A / FW6B / FW6C](protectli/fw6.md) -- [VP2420](protectli/vp2420.md) -- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md) +```{toctree} +:maxdepth: 1 + +FW2B / FW4B <protectli/fw2b_fw4b.md> +FW6A / FW6B / FW6C <protectli/fw6.md> +VP2420 <protectli/vp2420.md> +VP4630 / VP4650 / VP4670 <protectli/vp46xx.md> +``` ## Roda -- [RK9 Flash Header](roda/rk9/flash_header.md) +```{toctree} +:maxdepth: 1 + +RK9 Flash Header <roda/rk9/flash_header.md> +``` ## SiFive -- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) +```{toctree} +:maxdepth: 1 + +SiFive HiFive Unleashed <sifive/hifive-unleashed.md> +``` ## Star Labs Systems -- [LabTop Mk III](starlabs/labtop_kbl.md) -- [LabTop Mk IV](starlabs/labtop_cml.md) -- [StarLite Mk III](starlabs/lite_glk.md) -- [StarLite Mk IV](starlabs/lite_glkr.md) -- [StarBook Mk V](starlabs/starbook_tgl.md) -- [StarBook Mk VI](starlabs/starbook_adl.md) -- [Flashing devices](starlabs/common/flashing.md) +```{toctree} +:maxdepth: 1 + +LabTop Mk III <starlabs/labtop_kbl.md> +LabTop Mk IV <starlabs/labtop_cml.md> +StarLite Mk III <starlabs/lite_glk.md> +StarLite Mk IV <starlabs/lite_glkr.md> +StarBook Mk V <starlabs/starbook_tgl.md> +StarBook Mk VI <starlabs/starbook_adl.md> +Flashing devices <starlabs/common/flashing.md> +``` ## Supermicro -- [X9SAE](supermicro/x9sae.md) -- [X10SLM+-F](supermicro/x10slm-f.md) -- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md) -- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md) +```{toctree} +:maxdepth: 1 + +X9SAE <supermicro/x9sae.md> +X10SLM+-F <supermicro/x10slm-f.md> +X11 LGA1151 series <supermicro/x11-lga1151-series/x11-lga1151-series.md> +Flashing using the BMC <supermicro/flashing_on_vendorbmc.md> +``` ## System76 -- [Adder Workstation 1](system76/addw1.md) -- [Adder Workstation 2](system76/addw2.md) -- [Adder Workstation 3](system76/addw3.md) -- [Bonobo Workstation 14](system76/bonw14.md) -- [Bonobo Workstation 15](system76/bonw15.md) -- [Darter Pro 6](system76/darp6.md) -- [Darter Pro 7](system76/darp7.md) -- [Darter Pro 8](system76/darp8.md) -- [Darter Pro 9](system76/darp9.md) -- [Galago Pro 4](system76/galp4.md) -- [Galago Pro 5](system76/galp5.md) -- [Galago Pro 6](system76/galp6.md) -- [Galago Pro 7](system76/galp7.md) -- [Gazelle 15](system76/gaze15.md) -- [Gazelle 16](system76/gaze16.md) -- [Gazelle 17](system76/gaze17.md) -- [Gazelle 18](system76/gaze18.md) -- [Lemur Pro 9](system76/lemp9.md) -- [Lemur Pro 10](system76/lemp10.md) -- [Lemur Pro 11](system76/lemp11.md) -- [Lemur Pro 12](system76/lemp12.md) -- [Oryx Pro 5](system76/oryp5.md) -- [Oryx Pro 6](system76/oryp6.md) -- [Oryx Pro 7](system76/oryp7.md) -- [Oryx Pro 8](system76/oryp8.md) -- [Oryx Pro 9](system76/oryp9.md) -- [Oryx Pro 10](system76/oryp10.md) -- [Oryx Pro 11](system76/oryp11.md) -- [Serval Workstation 13](system76/serw13.md) +```{toctree} +:maxdepth: 1 + +Adder Workstation 1 <system76/addw1.md> +Adder Workstation 2 <system76/addw2.md> +Adder Workstation 3 <system76/addw3.md> +Bonobo Workstation 14 <system76/bonw14.md> +Bonobo Workstation 15 <system76/bonw15.md> +Darter Pro 6 <system76/darp6.md> +Darter Pro 7 <system76/darp7.md> +Darter Pro 8 <system76/darp8.md> +Darter Pro 9 <system76/darp9.md> +Galago Pro 4 <system76/galp4.md> +Galago Pro 5 <system76/galp5.md> +Galago Pro 6 <system76/galp6.md> +Galago Pro 7 <system76/galp7.md> +Gazelle 15 <system76/gaze15.md> +Gazelle 16 <system76/gaze16.md> +Gazelle 17 <system76/gaze17.md> +Gazelle 18 <system76/gaze18.md> +Lemur Pro 9 <system76/lemp9.md> +Lemur Pro 10 <system76/lemp10.md> +Lemur Pro 11 <system76/lemp11.md> +Lemur Pro 12 <system76/lemp12.md> +Oryx Pro 5 <system76/oryp5.md> +Oryx Pro 6 <system76/oryp6.md> +Oryx Pro 7 <system76/oryp7.md> +Oryx Pro 8 <system76/oryp8.md> +Oryx Pro 9 <system76/oryp9.md> +Oryx Pro 10 <system76/oryp10.md> +Oryx Pro 11 <system76/oryp11.md> +Serval Workstation 13 <system76/serw13.md> +``` ## Texas Instruments -- [Beaglebone Black](ti/beaglebone-black.md) +```{toctree} +:maxdepth: 1 + +Beaglebone Black <ti/beaglebone-black.md> +``` ## UP -- [Squared](up/squared/index.md) +```{toctree} +:maxdepth: 1 + +Squared <up/squared/index.md> +``` diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md index fac08bd..fe488a4 100644 --- a/Documentation/mainboard/intel/dg43gt.md +++ b/Documentation/mainboard/intel/dg43gt.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -79,7 +79,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+---------------------------------------------------+ | Northbridge | Intel G43 (called x4x in coreboot code) | +------------------+---------------------------------------------------+ diff --git a/Documentation/mainboard/intel/dq67sw.md b/Documentation/mainboard/intel/dq67sw.md index b3ed9b8..d641fc6 100644 --- a/Documentation/mainboard/intel/dq67sw.md +++ b/Documentation/mainboard/intel/dq67sw.md @@ -4,7 +4,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ @@ -67,7 +67,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -104,7 +104,7 @@ It is possible to program the chip is to attach an external programmer with an SOIC-8 clip. -```eval_rst +```{eval-rst} Another way is to boot the vendor firmware in UEFI mode and exploit the unpatched S3 Boot Script vulnerability. See this page for a similar procedure: :doc:`../lenovo/ivb_internal_flashing`. @@ -126,7 +126,7 @@ Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification prevents this by making it write a 0 instead. -```eval_rst +```{eval-rst} After suspending and resuming the board, the BIOS region can be flashed with a coreboot image, e.g. using flashrom. Note that the ME region is not readable, so the `--noverify-all` flag is necessary. Please refer to the diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md index d536bea..32cc5de 100644 --- a/Documentation/mainboard/intel/kblrvp11.md +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -23,7 +23,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -65,7 +65,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+---------------------------------------------------+ | CPU | Kaby lake H (i7-7820EQ) | +------------------+---------------------------------------------------+ diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md index e107864..62ef521 100644 --- a/Documentation/mainboard/kontron/mal10.md +++ b/Documentation/mainboard/kontron/mal10.md @@ -6,7 +6,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+----------------------------------+ | COMe Type | mini pin-out type 10 | +------------------+----------------------------------+ diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index bf49f5d..73d38fe 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -3,7 +3,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md). ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------------------+ | Type | Value | +=====================+================================+ @@ -37,7 +37,7 @@ exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. * ROM chip size should be set to 12MiB. -```eval_rst +```{eval-rst} Please also have a look at :doc:`../../tutorial/flashing_firmware/index`. ``` diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 2a53df3..0294aae 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -1,7 +1,7 @@ # Lenovo Sandy Bridge series ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------+ | Type | Value | +=====================+====================+ diff --git a/Documentation/mainboard/lenovo/codenames.md b/Documentation/mainboard/lenovo/codenames.md index 8552294..a5f70d6 100644 --- a/Documentation/mainboard/lenovo/codenames.md +++ b/Documentation/mainboard/lenovo/codenames.md @@ -1,6 +1,6 @@ # Lenovo mainboard codenames -```eval_rst +```{eval-rst} .. csv-table:: :header: "Marketing name", "Development codename" :file: codenames.csv diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index 40afd6f..a6004a7 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -19,7 +19,11 @@ - USB drive (in case you need to downgrade BIOS) - Linux install that (can be) loaded in UEFI mode -- [CHIPSEC](https://github.com/chipsec/chipsec) +```{toctree} +:maxdepth: 1 + +CHIPSEC <https://github.com/chipsec/chipsec> +``` ## BIOS versions @@ -27,7 +31,7 @@ goals, per model. The version number means that you need to downgrade to that or earlier version. -```eval_rst +```{eval-rst} +------------+--------------+ | Model | BIOS version | +============+==============+ diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 3ff2042..e4e5da3 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -20,7 +20,7 @@ ## Installing without ME firmware -```eval_rst +```{eval-rst} .. Note:: **ThinkPad R500** has slightly different flash layout (it doesn't have ``gbe`` region), so the process would be a little different for that model. @@ -51,7 +51,7 @@ Pick the layout according to your chip size from the table below and save it to the `new_layout.txt` file: -```eval_rst +```{eval-rst} +---------------------------+---------------------------+---------------------------+ | 4 MiB chip | 8 MiB chip | 16 MiB chip | +===========================+===========================+===========================+ @@ -102,7 +102,7 @@ If your flash is not 8 MiB, you need to change values of `flcomp_density1` and `flreg1_limit` in the `ifd-x200.set` file according to following table: -```eval_rst +```{eval-rst} +-----------------+-------+-------+--------+ | | 4 MiB | 8 MiB | 16 MiB | +=================+=======+=======+========+ @@ -144,7 +144,7 @@ The flash layouts of the OEM firmware are as follows: -```eval_rst +```{eval-rst} +---------------------------------+---------------------------------+ | 4 MiB chip | 8 MiB chip | +=================================+=================================+ diff --git a/Documentation/mainboard/lenovo/t410.md b/Documentation/mainboard/lenovo/t410.md index 80d54f8..0112607 100644 --- a/Documentation/mainboard/lenovo/t410.md +++ b/Documentation/mainboard/lenovo/t410.md @@ -5,7 +5,7 @@ * TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB) ## Flashing instructions -```eval_rst +```{eval-rst} +---------------------+--------------------------------+ | Type | Value | +=====================+================================+ diff --git a/Documentation/mainboard/libretrend/lt1000.md b/Documentation/mainboard/libretrend/lt1000.md index 78d5fc0..4b13d46 100644 --- a/Documentation/mainboard/libretrend/lt1000.md +++ b/Documentation/mainboard/libretrend/lt1000.md @@ -10,7 +10,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -98,7 +98,7 @@ sold yet). More details on [baseboard site]. Unfortunately the board manual is not publicly available. -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i7-6500U | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md index c92e674..4f4baf6 100644 --- a/Documentation/mainboard/msi/ms7707/ms7707.md +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -9,7 +9,7 @@ * IME 7.0.4.1197 ## Flash chip (Winbond 25Q32BV) -```eval_rst +```{eval-rst} +---------------------+--------------------+ | Type | Value | +=====================+====================+ diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index d4c0656..404052c 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -200,7 +200,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------------+---------------------------------------------+ | Processor (1 socket) | Intel Cooper Lake Scalable Processor | +------------------------+---------------------------------------------+ diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md index 8c49923..0cbf865 100644 --- a/Documentation/mainboard/ocp/tiogapass.md +++ b/Documentation/mainboard/ocp/tiogapass.md @@ -80,7 +80,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------------+---------------------------------------------+ | Processor (2 sockets) | Intel Skylake Scalable Processor LGA3647 | +------------------------+---------------------------------------------+ diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md index 02225a2..9fd30e8 100644 --- a/Documentation/mainboard/opencellular/elgon.md +++ b/Documentation/mainboard/opencellular/elgon.md @@ -9,7 +9,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ @@ -69,7 +69,7 @@ ## Technology -```eval_rst +```{eval-rst} +---------------+----------------------------------------+ | SoC | :doc:`../../soc/cavium/cn81xx/index` | +---------------+----------------------------------------+ diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md index ccadd63..fa59801 100644 --- a/Documentation/mainboard/pcengines/apu1.md +++ b/Documentation/mainboard/pcengines/apu1.md @@ -4,7 +4,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------+--------------------------------------------------------+ | CPU | AMD G series T40E APU | +------------+--------------------------------------------------------+ @@ -23,7 +23,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------------+ | Type | Value | +=====================+==========================+ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md index 4a02e12..caa26cc 100644 --- a/Documentation/mainboard/pcengines/apu2.md +++ b/Documentation/mainboard/pcengines/apu2.md @@ -4,7 +4,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------+---------------------------------------------------------------+ | CPU | AMD G series GX-412TC | +------------+---------------------------------------------------------------+ @@ -25,7 +25,7 @@ To build working coreboot image some blobs are needed. -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -41,7 +41,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+--------------------------+ | Type | Value | +=====================+==========================+ diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index 0350ac3..5d719ea 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -61,7 +61,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | SoC | Intel Atom Processor N3710 | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/prodrive/hermes.md b/Documentation/mainboard/prodrive/hermes.md index 3b73ee0..726382c 100644 --- a/Documentation/mainboard/prodrive/hermes.md +++ b/Documentation/mainboard/prodrive/hermes.md @@ -32,7 +32,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | CoffeeLake + CoffeeLake R (Core + Xeon) | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/protectli/fw2b_fw4b.md b/Documentation/mainboard/protectli/fw2b_fw4b.md index e7d5cbf..dec9909 100644 --- a/Documentation/mainboard/protectli/fw2b_fw4b.md +++ b/Documentation/mainboard/protectli/fw2b_fw4b.md @@ -9,7 +9,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -91,7 +91,7 @@ - FW2B: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Celeron J3060 | +------------------+--------------------------------------------------+ @@ -107,7 +107,7 @@ - FW4B: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Celeron J3160 | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md index 86449d1..6448486 100644 --- a/Documentation/mainboard/protectli/fw6.md +++ b/Documentation/mainboard/protectli/fw6.md @@ -9,7 +9,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -92,7 +92,7 @@ - FW6A: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Celeron 3865U | +------------------+--------------------------------------------------+ @@ -106,7 +106,7 @@ - FW6B: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i3-7100U | +------------------+--------------------------------------------------+ @@ -120,7 +120,7 @@ - FW6C: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i5-7200U | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md index 68b5da0d..b5a7ff6 100644 --- a/Documentation/mainboard/protectli/vp2420.md +++ b/Documentation/mainboard/protectli/vp2420.md @@ -10,7 +10,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -66,7 +66,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Celeron J6412 | +------------------+--------------------------------------------------+ @@ -80,8 +80,12 @@ ## Useful links -- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/) -- [VP2420 Product Page](https://protectli.com/product/vp2420/) -- [Protectli TPM module](https://protectli.com/product/tpm-module/) -- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf) -- [flashrom](https://flashrom.org/Flashrom) +```{toctree} +:maxdepth: 1 + +VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/> +VP2420 Product Page <https://protectli.com/product/vp2420/> +Protectli TPM module <https://protectli.com/product/tpm-module/> +MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,…> +flashrom <https://flashrom.org/Flashrom> +``` diff --git a/Documentation/mainboard/protectli/vp46xx.md b/Documentation/mainboard/protectli/vp46xx.md index 12accb5..eada7ff 100644 --- a/Documentation/mainboard/protectli/vp46xx.md +++ b/Documentation/mainboard/protectli/vp46xx.md @@ -10,7 +10,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ @@ -84,7 +84,7 @@ - VP4630: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i3-10110U | +------------------+--------------------------------------------------+ @@ -98,7 +98,7 @@ - VP4650: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i5-10210U | +------------------+--------------------------------------------------+ @@ -112,7 +112,7 @@ - VP4670: -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i7-10810U | +------------------+--------------------------------------------------+ @@ -126,9 +126,13 @@ ## Useful links -- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/) -- [VP4630 Product Page](https://protectli.com/product/vp4630/) -- [Protectli TPM module](https://protectli.com/product/tpm-module/) +```{toctree} +:maxdepth: 1 + +VP4600 Hardware Overview <https://protectli.com/kb/vp4600-hardware-overview/> +VP4630 Product Page <https://protectli.com/product/vp4630/> +Protectli TPM module <https://protectli.com/product/tpm-module/> +``` [Protectli VP46xx]: https://protectli.com/vault-6-port/ [MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,… diff --git a/Documentation/mainboard/purism/librem_14.md b/Documentation/mainboard/purism/librem_14.md index 777e909..22bb183 100644 --- a/Documentation/mainboard/purism/librem_14.md +++ b/Documentation/mainboard/purism/librem_14.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the [Purism Librem 14]. -```eval_rst +```{eval-rst} +------------------+------------------------------------------------------+ | CPU | Intel Core i7-10710U | +------------------+------------------------------------------------------+ @@ -23,7 +23,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md index 0e1fbd0..39cfca9 100644 --- a/Documentation/mainboard/purism/librem_mini.md +++ b/Documentation/mainboard/purism/librem_mini.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the [Purism Librem Mini]. -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Core i7-8565U/8665U (v1) | | | Intel Core i7-10510U (v2) | @@ -25,7 +25,7 @@ To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified). -```eval_rst +```{eval-rst} +-----------------+---------------------------------+---------------------+ | Binary file | Apply | Required / Optional | +=================+=================================+=====================+ diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md index f568d2b..d9fdba5 100644 --- a/Documentation/mainboard/starlabs/labtop_cml.md +++ b/Documentation/mainboard/starlabs/labtop_cml.md @@ -45,7 +45,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/starlabs/labtop_kbl.md b/Documentation/mainboard/starlabs/labtop_kbl.md index 89a5001..eb68938 100644 --- a/Documentation/mainboard/starlabs/labtop_kbl.md +++ b/Documentation/mainboard/starlabs/labtop_kbl.md @@ -42,7 +42,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/starlabs/lite_glk.md b/Documentation/mainboard/starlabs/lite_glk.md index 849d3a8..d31b680 100644 --- a/Documentation/mainboard/starlabs/lite_glk.md +++ b/Documentation/mainboard/starlabs/lite_glk.md @@ -41,7 +41,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/starlabs/lite_glkr.md b/Documentation/mainboard/starlabs/lite_glkr.md index 410747b..bf36281 100644 --- a/Documentation/mainboard/starlabs/lite_glkr.md +++ b/Documentation/mainboard/starlabs/lite_glkr.md @@ -41,7 +41,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/starlabs/starbook_adl.md b/Documentation/mainboard/starlabs/starbook_adl.md index 6ca956b..cce9cbe 100644 --- a/Documentation/mainboard/starlabs/starbook_adl.md +++ b/Documentation/mainboard/starlabs/starbook_adl.md @@ -78,7 +78,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/starlabs/starbook_tgl.md b/Documentation/mainboard/starlabs/starbook_tgl.md index 58be26f..30810dd 100644 --- a/Documentation/mainboard/starlabs/starbook_tgl.md +++ b/Documentation/mainboard/starlabs/starbook_tgl.md @@ -44,7 +44,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 97c78d6..70e6e0a 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -4,13 +4,13 @@ ## Required proprietary blobs -```eval_rst +```{eval-rst} Please see :doc:`../../northbridge/intel/haswell/mrc.bin`. ``` ## Building coreboot -```eval_rst +```{eval-rst} If you haven't already, build the coreboot toolchain as described in :doc:`../../tutorial/part1`. ``` @@ -40,7 +40,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} In addition to the information here, please see the :doc:`../../tutorial/flashing_firmware/index`. ``` @@ -119,7 +119,7 @@ ## ECC DRAM -```eval_rst +```{eval-rst} ECC DRAM seems to work, but please see :doc:`../../northbridge/intel/haswell/mrc.bin` for caveats. @@ -139,7 +139,7 @@ in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS, and hence the OS can do fan control. -```eval_rst +```{eval-rst} Please also see :doc:`../../northbridge/intel/haswell/known-issues`. ``` @@ -176,7 +176,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | :doc:`../../northbridge/intel/haswell/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 109885c..206f7f9 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -6,10 +6,14 @@ ## Supported boards -- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) -- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md) -- [X11SSM-F](x11ssm-f/x11ssm-f.md) -- [X11SSW-F](x11ssw-f/x11ssw-f.md) +```{toctree} +:maxdepth: 1 + +X11SSH-TF <x11ssh-tf/x11ssh-tf.md> +X11SSH-F/LN4F <x11ssh-f/x11ssh-f.md> +X11SSM-F <x11ssm-f/x11ssm-f.md> +X11SSW-F <x11ssw-f/x11ssw-f.md> +``` ## Required proprietary blobs @@ -42,7 +46,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Kaby Lake | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md index 35b552f..836c733 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -55,7 +55,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Kaby Lake | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md index 1616676..963cf71 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -35,7 +35,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Kaby Lake | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md index 4e42809..3625a56 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md @@ -46,7 +46,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Kaby Lake | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md index 8164df1..5b25643 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md @@ -31,7 +31,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | CPU | Intel Kaby Lake | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/supermicro/x9sae.md b/Documentation/mainboard/supermicro/x9sae.md index 406785d..df55950 100644 --- a/Documentation/mainboard/supermicro/x9sae.md +++ b/Documentation/mainboard/supermicro/x9sae.md @@ -4,7 +4,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+----------------+ | Type | Value | +=====================+================+ @@ -81,7 +81,7 @@ ## Technology -```eval_rst +```{eval-rst} +------------------+--------------------------------------------------+ | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | +------------------+--------------------------------------------------+ diff --git a/Documentation/mainboard/system76/addw1.md b/Documentation/mainboard/system76/addw1.md index 332070a..5d5dae3 100644 --- a/Documentation/mainboard/system76/addw1.md +++ b/Documentation/mainboard/system76/addw1.md @@ -44,7 +44,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/addw2.md b/Documentation/mainboard/system76/addw2.md index a5015de..9a302a2 100644 --- a/Documentation/mainboard/system76/addw2.md +++ b/Documentation/mainboard/system76/addw2.md @@ -43,7 +43,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/addw3.md b/Documentation/mainboard/system76/addw3.md index c964351..dccd630 100644 --- a/Documentation/mainboard/system76/addw3.md +++ b/Documentation/mainboard/system76/addw3.md @@ -48,7 +48,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/bonw14.md b/Documentation/mainboard/system76/bonw14.md index 2ea866b..cc94f39 100644 --- a/Documentation/mainboard/system76/bonw14.md +++ b/Documentation/mainboard/system76/bonw14.md @@ -53,7 +53,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/bonw15.md b/Documentation/mainboard/system76/bonw15.md index db32efe..63c00d9 100644 --- a/Documentation/mainboard/system76/bonw15.md +++ b/Documentation/mainboard/system76/bonw15.md @@ -42,7 +42,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/darp6.md b/Documentation/mainboard/system76/darp6.md index 3643014..152727f 100644 --- a/Documentation/mainboard/system76/darp6.md +++ b/Documentation/mainboard/system76/darp6.md @@ -40,7 +40,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/darp7.md b/Documentation/mainboard/system76/darp7.md index d1dee86..06cf034 100644 --- a/Documentation/mainboard/system76/darp7.md +++ b/Documentation/mainboard/system76/darp7.md @@ -42,7 +42,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/darp8.md b/Documentation/mainboard/system76/darp8.md index 4d2da37..1dadc4f 100644 --- a/Documentation/mainboard/system76/darp8.md +++ b/Documentation/mainboard/system76/darp8.md @@ -40,7 +40,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ @@ -59,7 +59,7 @@ | External flashing | yes | +---------------------+---------------------+ ``` -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/darp9.md b/Documentation/mainboard/system76/darp9.md index b0f1566..f7d299d 100644 --- a/Documentation/mainboard/system76/darp9.md +++ b/Documentation/mainboard/system76/darp9.md @@ -39,7 +39,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/galp4.md b/Documentation/mainboard/system76/galp4.md index aa661fe..bd8919c 100644 --- a/Documentation/mainboard/system76/galp4.md +++ b/Documentation/mainboard/system76/galp4.md @@ -42,7 +42,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/galp5.md b/Documentation/mainboard/system76/galp5.md index 8284050..440e387 100644 --- a/Documentation/mainboard/system76/galp5.md +++ b/Documentation/mainboard/system76/galp5.md @@ -45,7 +45,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/galp6.md b/Documentation/mainboard/system76/galp6.md index e519dc3..a6c103e 100644 --- a/Documentation/mainboard/system76/galp6.md +++ b/Documentation/mainboard/system76/galp6.md @@ -38,7 +38,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/galp7.md b/Documentation/mainboard/system76/galp7.md index 3d27716..41624ca 100644 --- a/Documentation/mainboard/system76/galp7.md +++ b/Documentation/mainboard/system76/galp7.md @@ -35,7 +35,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/gaze15.md b/Documentation/mainboard/system76/gaze15.md index facdae6..45e4e26 100644 --- a/Documentation/mainboard/system76/gaze15.md +++ b/Documentation/mainboard/system76/gaze15.md @@ -51,7 +51,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/gaze16.md b/Documentation/mainboard/system76/gaze16.md index d8bc7ca..a680a5c 100644 --- a/Documentation/mainboard/system76/gaze16.md +++ b/Documentation/mainboard/system76/gaze16.md @@ -64,7 +64,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/gaze17.md b/Documentation/mainboard/system76/gaze17.md index cf7f0a2..1456f9f 100644 --- a/Documentation/mainboard/system76/gaze17.md +++ b/Documentation/mainboard/system76/gaze17.md @@ -39,7 +39,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/gaze18.md b/Documentation/mainboard/system76/gaze18.md index fe564e8..5c3212a 100644 --- a/Documentation/mainboard/system76/gaze18.md +++ b/Documentation/mainboard/system76/gaze18.md @@ -49,7 +49,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/lemp10.md b/Documentation/mainboard/system76/lemp10.md index 89e57b5..b0888af 100644 --- a/Documentation/mainboard/system76/lemp10.md +++ b/Documentation/mainboard/system76/lemp10.md @@ -40,7 +40,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/lemp11.md b/Documentation/mainboard/system76/lemp11.md index f05d63a..acb791b 100644 --- a/Documentation/mainboard/system76/lemp11.md +++ b/Documentation/mainboard/system76/lemp11.md @@ -39,7 +39,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/lemp12.md b/Documentation/mainboard/system76/lemp12.md index 55a2e35..a095bad 100644 --- a/Documentation/mainboard/system76/lemp12.md +++ b/Documentation/mainboard/system76/lemp12.md @@ -39,7 +39,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/lemp9.md b/Documentation/mainboard/system76/lemp9.md index 9739484..c216188 100644 --- a/Documentation/mainboard/system76/lemp9.md +++ b/Documentation/mainboard/system76/lemp9.md @@ -52,7 +52,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/mainboard/system76/oryp10.md b/Documentation/mainboard/system76/oryp10.md index 921585c..40872e3 100644 --- a/Documentation/mainboard/system76/oryp10.md +++ b/Documentation/mainboard/system76/oryp10.md @@ -46,7 +46,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/oryp11.md b/Documentation/mainboard/system76/oryp11.md index ad0a54e..bd86632 100644 --- a/Documentation/mainboard/system76/oryp11.md +++ b/Documentation/mainboard/system76/oryp11.md @@ -43,7 +43,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/oryp5.md b/Documentation/mainboard/system76/oryp5.md index 662581c..bfde6c0 100644 --- a/Documentation/mainboard/system76/oryp5.md +++ b/Documentation/mainboard/system76/oryp5.md @@ -47,7 +47,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/oryp6.md b/Documentation/mainboard/system76/oryp6.md index 2c1975e..6a52c54 100644 --- a/Documentation/mainboard/system76/oryp6.md +++ b/Documentation/mainboard/system76/oryp6.md @@ -37,7 +37,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/oryp7.md b/Documentation/mainboard/system76/oryp7.md index 4672d67..6496aea 100644 --- a/Documentation/mainboard/system76/oryp7.md +++ b/Documentation/mainboard/system76/oryp7.md @@ -48,7 +48,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/oryp8.md b/Documentation/mainboard/system76/oryp8.md index cfd59d0..53eb446 100644 --- a/Documentation/mainboard/system76/oryp8.md +++ b/Documentation/mainboard/system76/oryp8.md @@ -47,7 +47,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+-----------------+ | Type | Value | +=====================+=================+ diff --git a/Documentation/mainboard/system76/oryp9.md b/Documentation/mainboard/system76/oryp9.md index 87e176b..33ccf00 100644 --- a/Documentation/mainboard/system76/oryp9.md +++ b/Documentation/mainboard/system76/oryp9.md @@ -44,7 +44,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/system76/serw13.md b/Documentation/mainboard/system76/serw13.md index 6b56a39..0695c8f 100644 --- a/Documentation/mainboard/system76/serw13.md +++ b/Documentation/mainboard/system76/serw13.md @@ -46,7 +46,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+---------------------+ | Type | Value | +=====================+=====================+ diff --git a/Documentation/mainboard/ti/beaglebone-black.md b/Documentation/mainboard/ti/beaglebone-black.md index 7fc6762..3608618 100644 --- a/Documentation/mainboard/ti/beaglebone-black.md +++ b/Documentation/mainboard/ti/beaglebone-black.md @@ -56,7 +56,7 @@ The pin mapping is shown below for J1. - ```eval_rst + ```{eval-rst} +----------------------------+------------+ | Pin number | Function | +============================+============+ diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md index 2895e1f..f402095 100644 --- a/Documentation/mainboard/up/squared/index.md +++ b/Documentation/mainboard/up/squared/index.md @@ -15,7 +15,7 @@ ## Mainboard components ### Platform -```eval_rst +```{eval-rst} +------------------+----------------------------------+ | CPU | Intel Atom, Celeron, Pentium | +------------------+----------------------------------+ @@ -28,7 +28,7 @@ ``` ### Flash chip -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ diff --git a/Documentation/northbridge/index.md b/Documentation/northbridge/index.md index 7970078..e89a24b 100644 --- a/Documentation/northbridge/index.md +++ b/Documentation/northbridge/index.md @@ -4,4 +4,8 @@ ## Vendor -- [Intel](intel/index.md) +```{toctree} +:maxdepth: 1 + +Intel <intel/index.md> +``` diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md index 87fb56f..e7601d1 100644 --- a/Documentation/northbridge/intel/haswell/index.md +++ b/Documentation/northbridge/intel/haswell/index.md @@ -5,8 +5,16 @@ ## Proprietary blobs -- [mrc.bin](mrc.bin.md) +```{toctree} +:maxdepth: 1 + +mrc.bin <mrc.bin.md> +``` ## Issues -- [Known issues](known-issues.md) +```{toctree} +:maxdepth: 1 + +Known issues <known-issues.md> +``` diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md index c684b8f..e049a94 100644 --- a/Documentation/northbridge/intel/haswell/known-issues.md +++ b/Documentation/northbridge/intel/haswell/known-issues.md @@ -5,7 +5,7 @@ ## PCIe graphics -```eval_rst +```{eval-rst} Using a PCIe graphics card for display output is not currently supported. This is because :doc:`./mrc.bin` requires workarounds to have such a feature working correctly. diff --git a/Documentation/northbridge/intel/index.md b/Documentation/northbridge/intel/index.md index da7634b..2eec6a4 100644 --- a/Documentation/northbridge/intel/index.md +++ b/Documentation/northbridge/intel/index.md @@ -4,5 +4,9 @@ ## Platforms -- [Haswell](haswell/index.md) -- [Sandy Bridge](sandybridge/index.md) +```{toctree} +:maxdepth: 1 + +Haswell <haswell/index.md> +Sandy Bridge <sandybridge/index.md> +``` diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index 27fbb2cc2..461fa8f 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -4,6 +4,10 @@ ## Topics -- [Native RAM Initialization](nri.md) -- [RAM initialization feature matrix](nri_features.md) -- [ME Cleaner](me_cleaner.md) +```{toctree} +:maxdepth: 1 + +Native RAM Initialization <nri.md> +RAM initialization feature matrix <nri_features.md> +ME Cleaner <me_cleaner.md> +``` diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 1cd5fb4..6327282 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -18,7 +18,7 @@ * Error handling ## Definitions -```eval_rst +```{eval-rst} +---------+-------------------------------------------------------------------+------------+--------------+ | Symbol | Description | Units | Valid region | +=========+===================================================================+============+==============+ @@ -41,13 +41,25 @@ ``` ## (Unofficial) register documentation -- [Sandy Bridge - Register documentation](nri_registers.md) +```{toctree} +:maxdepth: 1 + +Sandy Bridge - Register documentation <nri_registers.md> +``` ## Frequency selection -- [Sandy Bridge - Frequency selection](nri_freq.md) +```{toctree} +:maxdepth: 1 + +Sandy Bridge - Frequency selection <nri_freq.md> +``` ## Read training -- [Sandy Bridge - Read training](nri_read.md) +```{toctree} +:maxdepth: 1 + +Sandy Bridge - Read training <nri_read.md> +``` ### SMBIOS type 17 The SMBIOS specification allows to report the memory configuration in use. diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md index 670fcb6..386738b 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_features.md +++ b/Documentation/northbridge/intel/sandybridge/nri_features.md @@ -14,7 +14,7 @@ ## Native raminit implemented features -```eval_rst +```{eval-rst} +---------------------------+----------------------+-------------+---------+---------------------+ | Option | Supported | Implemented | Working | Comments | +===========================+======================+=============+=========+=====================+ diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 8d66b5c..45cac8d 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -5,7 +5,7 @@ Bridge memory initialization. ## Definitions -```eval_rst +```{eval-rst} +---------+-------------------------------------------------------------------+------------+--------------+ | Symbol | Description | Units | Valid region | +=========+===================================================================+============+==============+ @@ -94,7 +94,7 @@ > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK. ## Sandy Bridge's supported frequencies -```eval_rst +```{eval-rst} +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | +============+===========+==================+=========================+===============+ @@ -113,7 +113,7 @@ ``` ## Ivy Bridge's supported frequencies -```eval_rst +```{eval-rst} +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | +============+===========+==================+=========================+===============+ diff --git a/Documentation/northbridge/intel/sandybridge/nri_read.md b/Documentation/northbridge/intel/sandybridge/nri_read.md index f5c79ac..af03d56 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_read.md +++ b/Documentation/northbridge/intel/sandybridge/nri_read.md @@ -23,7 +23,7 @@ The values programmed in read training effect DRAM-to-MC transfers only ! ## Definitions -```eval_rst +```{eval-rst} +---------+-------------------------------------------------------------------+------------+--------------+ | Symbol | Description | Units | Valid region | +=========+===================================================================+============+==============+ diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 6abf5c9..750e755 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -11,7 +11,7 @@ *Desc:* Lane training result Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -26,7 +26,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -46,7 +46,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -66,7 +66,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -86,7 +86,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -106,7 +106,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -126,7 +126,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -146,7 +146,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -166,7 +166,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -186,7 +186,7 @@ *Desc:* Lane training result Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -201,7 +201,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -221,7 +221,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -241,7 +241,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -261,7 +261,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -281,7 +281,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -301,7 +301,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -321,7 +321,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -341,7 +341,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -361,7 +361,7 @@ *Desc:* Lane training result Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -376,7 +376,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -396,7 +396,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -416,7 +416,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -436,7 +436,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -456,7 +456,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -476,7 +476,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -496,7 +496,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -516,7 +516,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -536,7 +536,7 @@ *Desc:* Lane training result Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -551,7 +551,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -571,7 +571,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -591,7 +591,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -611,7 +611,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -631,7 +631,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -651,7 +651,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -671,7 +671,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -691,7 +691,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -711,7 +711,7 @@ *Desc:* Lane training result Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -726,7 +726,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -746,7 +746,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -766,7 +766,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -786,7 +786,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -806,7 +806,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -826,7 +826,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -846,7 +846,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -866,7 +866,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 4 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -886,7 +886,7 @@ *Desc:* Lane training result Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -901,7 +901,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -921,7 +921,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -941,7 +941,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -961,7 +961,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -981,7 +981,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1001,7 +1001,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1021,7 +1021,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1041,7 +1041,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 5 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1061,7 +1061,7 @@ *Desc:* Lane training result Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1076,7 +1076,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1096,7 +1096,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1126,7 +1126,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1154,7 +1154,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1174,7 +1174,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1194,7 +1194,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1214,7 +1214,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1234,7 +1234,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 6 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1254,7 +1254,7 @@ *Desc:* Lane training result Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1269,7 +1269,7 @@ *Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1289,7 +1289,7 @@ *Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1309,7 +1309,7 @@ *Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1329,7 +1329,7 @@ *Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1349,7 +1349,7 @@ *Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1369,7 +1369,7 @@ *Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1389,7 +1389,7 @@ *Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1409,7 +1409,7 @@ *Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 7 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1429,7 +1429,7 @@ *Desc:* COMP1 Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1447,7 +1447,7 @@ *Desc:* Command crossover enable Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1469,7 +1469,7 @@ *Desc:* COMP2 Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1483,7 +1483,7 @@ *Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1505,7 +1505,7 @@ *Desc:* TC_RAP - Timing of DDR - Regular Access Parameters Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1545,7 +1545,7 @@ *Desc:* OTHP ODT control Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1565,7 +1565,7 @@ *Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1581,7 +1581,7 @@ *Desc:* Rounttrip time Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1601,7 +1601,7 @@ *Desc:* SC_IO_LATENCY Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1623,7 +1623,7 @@ *Desc:* RAM training queue, address Register, Channel 0, queue idx 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1641,7 +1641,7 @@ *Desc:* RAM training queue, address Register, Channel 0, queue idx 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1659,7 +1659,7 @@ *Desc:* RAM training queue, address Register, Channel 0, queue idx 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1677,7 +1677,7 @@ *Desc:* RAM training queue, address Register, Channel 0, queue idx 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1695,7 +1695,7 @@ *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1713,7 +1713,7 @@ *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1731,7 +1731,7 @@ *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1749,7 +1749,7 @@ *Desc:* RAM training queue, command IO Register, Channel 0, queue idx 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1767,7 +1767,7 @@ *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1781,7 +1781,7 @@ *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 1 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1795,7 +1795,7 @@ *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 2 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1809,7 +1809,7 @@ *Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 3 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1823,7 +1823,7 @@ *Desc:* RAM training queue, cooldown Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1839,7 +1839,7 @@ *Desc:* TC - Refresh parameters Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1859,7 +1859,7 @@ *Desc:* SRFTP Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1879,7 +1879,7 @@ *Desc:* Scheduler parameters Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1893,7 +1893,7 @@ *Desc:* PM - Power-down configuration, Broadcast Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1929,7 +1929,7 @@ *Desc:* Power mode preset Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1943,7 +1943,7 @@ *Desc:* TC - Refresh parameters Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1964,7 +1964,7 @@ *Desc:* TC - Refresh parameters Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -1984,7 +1984,7 @@ *Desc:* Global channel size control Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2023,7 +2023,7 @@ *Desc:* Address Decode Register, Channel 0 -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2072,7 +2072,7 @@ *Desc:* Global DDR3 control Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2090,7 +2090,7 @@ *Desc:* Version Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2104,7 +2104,7 @@ *Desc:* PM - Self refresh config Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2123,7 +2123,7 @@ *Desc:* RCOMP status Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2137,7 +2137,7 @@ *Desc:* ECC - Address compare for ECC error injection Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2151,7 +2151,7 @@ *Desc:* ECC - Address mask for ECC error injection Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2168,7 +2168,7 @@ *Desc:* MC_BIOS_REQ Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2189,7 +2189,7 @@ *Desc:* MC_BIOS_DATA Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ @@ -2208,7 +2208,7 @@ *Desc:* RCOMP control Register -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ diff --git a/Documentation/releases/boards_supported_on_branches.md b/Documentation/releases/boards_supported_on_branches.md index ad7f356..6da7412 100644 --- a/Documentation/releases/boards_supported_on_branches.md +++ b/Documentation/releases/boards_supported_on_branches.md @@ -26,7 +26,7 @@ ## [4.19 Release](coreboot-4.19-relnotes.md) Branch created, builder configured -```eval_rst +```{eval-rst} +-------------------------------+------------------------+------------+-----------+ | Vendor/Board | Processor | Date added | Brd type | +===============================+========================+============+===========+ @@ -37,7 +37,7 @@ ## [4.18 Release](coreboot-4.18-relnotes.md) Branch created, builder configured -```eval_rst +```{eval-rst} +-------------------------------+------------------------+------------+-----------+ | Vendor/Board | Processor | Date added | Brd type | +===============================+========================+============+===========+ @@ -120,7 +120,7 @@ ## [4.13 Release](coreboot-4.13-relnotes.md) Tag only -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -132,7 +132,7 @@ Branch created, builder configured -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -148,7 +148,7 @@ Branch created, builder configured -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -251,7 +251,7 @@ ## [4.10 Release](coreboot-4.10-relnotes.md) Branch created -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -263,7 +263,7 @@ ## [4.9 Release](coreboot-4.9-relnotes.md) Tag only -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -281,7 +281,7 @@ ## [4.8.1 Release](coreboot-4.8.1-relnotes.md) Branch created -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -417,7 +417,7 @@ ## [4.7 Release](coreboot-4.7-relnotes.md) Tag only -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -504,7 +504,7 @@ ## [4.6](coreboot-4.6-relnotes.md) Tag only -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -520,7 +520,7 @@ ## [4.5](coreboot-4.5-relnotes.md) Tag only -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -548,7 +548,7 @@ ## [4.4](coreboot-4.4-relnotes.md) Branch created -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ @@ -574,7 +574,7 @@ ## [4.2](coreboot-4.2-relnotes.md) Branch created -```eval_rst +```{eval-rst} +-----------------------------+------------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=============================+========================+============+==========+ diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 2d33487..29ebdbb 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -1,4 +1,4 @@ -```eval_rst +```{eval-rst} :orphan: ``` diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md index eb136f4..2ad45ca 100644 --- a/Documentation/releases/coreboot-4.17-relnotes.md +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -12,7 +12,11 @@ Major Bugfixes in this release ------------------------------ -* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-292… +```{toctree} +:maxdepth: 1 + +CVE-2022-29264 <https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264> +``` New Mainboards diff --git a/Documentation/releases/coreboot-4.19-relnotes.md b/Documentation/releases/coreboot-4.19-relnotes.md index f0ef10d..09e99f6 100644 --- a/Documentation/releases/coreboot-4.19-relnotes.md +++ b/Documentation/releases/coreboot-4.19-relnotes.md @@ -221,7 +221,7 @@ --------------------------------- Issues from the coreboot bugtracker: https://ticket.coreboot.org/ -```eval_rst +```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ diff --git a/Documentation/releases/coreboot-4.20.1-relnotes.md b/Documentation/releases/coreboot-4.20.1-relnotes.md index 3bfa993..6f41100 100644 --- a/Documentation/releases/coreboot-4.20.1-relnotes.md +++ b/Documentation/releases/coreboot-4.20.1-relnotes.md @@ -230,7 +230,7 @@ --------------------------------- Issues from the coreboot bugtracker: https://ticket.coreboot.org/ -```eval_rst +```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index 9bc1b6d..5e493b5 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -356,7 +356,7 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/ -```eval_rst +```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index 4cd0991..a36bc81 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -267,7 +267,7 @@ ### Payload-specific issues -```eval_rst +```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ @@ -284,7 +284,7 @@ ### Platform-specific issues -```eval_rst +```{eval-rst} +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 17a9462..da7dc46 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -3,7 +3,11 @@ ## Upcoming release Please add to the release notes as changes are added: -* [24.05 - May 2024](coreboot-24.05-relnotes.md) +```{toctree} +:maxdepth: 1 + +24.05 - May 2024 <coreboot-24.05-relnotes.md> +``` The [checklist] contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -15,29 +19,33 @@ ## Previous releases -* [24.02 - February 2024](coreboot-24.02-relnotes.md) -* [4.22 - November 2023](coreboot-4.22-relnotes.md) -* [4.21 - August 2023](coreboot-4.21-relnotes.md) -* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md) -* [4.19 - January 2023](coreboot-4.19-relnotes.md) -* [4.18 - October 2022](coreboot-4.18-relnotes.md) -* [4.17 - May 2022](coreboot-4.17-relnotes.md) -* [4.16 - February 2022](coreboot-4.16-relnotes.md) -* [4.15 - November 2021](coreboot-4.15-relnotes.md) -* [4.14 - May 2021](coreboot-4.14-relnotes.md) -* [4.13 - November 2020](coreboot-4.13-relnotes.md) -* [4.12 - May 2020](coreboot-4.12-relnotes.md) -* [4.11 - November 2019](coreboot-4.11-relnotes.md) -* [4.10 - July 2019](coreboot-4.10-relnotes.md) -* [4.9 - December 2018](coreboot-4.9-relnotes.md) -* [4.8.1 - May 2018](coreboot-4.8.1-relnotes.md) -* [4.7 - January 2018](coreboot-4.7-relnotes.md) -* [4.6 - April 2017](coreboot-4.6-relnotes.md) -* [4.5 - October 2016](coreboot-4.5-relnotes.md) -* [4.4 - May 2016](coreboot-4.4-relnotes.md) -* [4.3 - January 2016](coreboot-4.3-relnotes.md) -* [4.2 - October 2015](coreboot-4.2-relnotes.md) -* [4.1 - July 2015](coreboot-4.1-relnotes.md) +```{toctree} +:maxdepth: 1 + +24.02 - February 2024 <coreboot-24.02-relnotes.md> +4.22 - November 2023 <coreboot-4.22-relnotes.md> +4.21 - August 2023 <coreboot-4.21-relnotes.md> +4.20.1 - May 2023 <coreboot-4.20.1-relnotes.md> +4.19 - January 2023 <coreboot-4.19-relnotes.md> +4.18 - October 2022 <coreboot-4.18-relnotes.md> +4.17 - May 2022 <coreboot-4.17-relnotes.md> +4.16 - February 2022 <coreboot-4.16-relnotes.md> +4.15 - November 2021 <coreboot-4.15-relnotes.md> +4.14 - May 2021 <coreboot-4.14-relnotes.md> +4.13 - November 2020 <coreboot-4.13-relnotes.md> +4.12 - May 2020 <coreboot-4.12-relnotes.md> +4.11 - November 2019 <coreboot-4.11-relnotes.md> +4.10 - July 2019 <coreboot-4.10-relnotes.md> +4.9 - December 2018 <coreboot-4.9-relnotes.md> +4.8.1 - May 2018 <coreboot-4.8.1-relnotes.md> +4.7 - January 2018 <coreboot-4.7-relnotes.md> +4.6 - April 2017 <coreboot-4.6-relnotes.md> +4.5 - October 2016 <coreboot-4.5-relnotes.md> +4.4 - May 2016 <coreboot-4.4-relnotes.md> +4.3 - January 2016 <coreboot-4.3-relnotes.md> +4.2 - October 2015 <coreboot-4.2-relnotes.md> +4.1 - July 2015 <coreboot-4.1-relnotes.md> +``` [checklist]: checklist.md diff --git a/Documentation/releases/templates.md b/Documentation/releases/templates.md index adc9d66..897f1ad 100644 --- a/Documentation/releases/templates.md +++ b/Documentation/releases/templates.md @@ -1,4 +1,4 @@ -```eval_rst +```{eval-rst} :orphan: ``` diff --git a/Documentation/security/index.md b/Documentation/security/index.md index c9cb4a7..0b5ef5f 100644 --- a/Documentation/security/index.md +++ b/Documentation/security/index.md @@ -4,16 +4,28 @@ ## Vendor -- [Verified Boot](vboot/index.md) -- [Measured Boot](vboot/measured_boot.md) -- [Memory clearing](memory_clearing.md) +```{toctree} +:maxdepth: 1 + +Verified Boot <vboot/index.md> +Measured Boot <vboot/measured_boot.md> +Memory clearing <memory_clearing.md> +``` ## Intel TXT -- [Intel TXT in general](intel/txt.md) -- [Intel TXT Initial Boot Block](intel/txt_ibb.md) -- [Intel Authenticated Code Modules](intel/acm.md) +```{toctree} +:maxdepth: 1 + +Intel TXT in general <intel/txt.md> +Intel TXT Initial Boot Block <intel/txt_ibb.md> +Intel Authenticated Code Modules <intel/acm.md> +``` ## SMM -- [System Management Mode](smm.md) +```{toctree} +:maxdepth: 1 + +System Management Mode <smm.md> +``` diff --git a/Documentation/security/memory_clearing.md b/Documentation/security/memory_clearing.md index e5c1925..6a058ff 100644 --- a/Documentation/security/memory_clearing.md +++ b/Documentation/security/memory_clearing.md @@ -45,4 +45,8 @@ ## Architecture specific implementations -* [x86 PAE](../arch/x86/pae.md) +```{toctree} +:maxdepth: 1 + +x86 PAE <../arch/x86/pae.md> +``` diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 1a17c20..957009e 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -12,7 +12,11 @@ Google's vboot verifies the firmware and places measurements within the TPM. -- [List of supported Devices](list_vboot.md) +```{toctree} +:maxdepth: 1 + +List of supported Devices <list_vboot.md> +``` *** diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index e4fa6c9..0ad8816 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -4,10 +4,18 @@ ## Technology -- [Family 15h](family15h.md) -- [Family 17h](family17h.md) -- [Platform Security Processor Integration](psp_integration.md) +```{toctree} +:maxdepth: 1 + +Family 15h <family15h.md> +Family 17h <family17h.md> +Platform Security Processor Integration <psp_integration.md> +``` ## amd_blobs Repository License -- [amd_blobs](amdblobs_license.md) +```{toctree} +:maxdepth: 1 + +amd_blobs <amdblobs_license.md> +``` diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md index 8e27f59..74f35b9 100644 --- a/Documentation/soc/amd/psp_integration.md +++ b/Documentation/soc/amd/psp_integration.md @@ -37,7 +37,7 @@ structure (for all families combined). Individual features supported vary by family and model. -```eval_rst +```{eval-rst} +--------------+---------------+------------------+----------------------------+ | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | +==============+===============+==================+============================+ @@ -85,7 +85,7 @@ implementations currently use combo tables. ### PSP Directory Table Header -```eval_rst +```{eval-rst} +--------------+---------------+------------------+----------------------------+ | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | +==============+===============+==================+============================+ @@ -105,7 +105,7 @@ ``` ### PSP Directory Table Entries -```eval_rst +```{eval-rst} +--------------+---------------+------------------+----------------------------+ | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | +==============+===============+==================+============================+ @@ -260,7 +260,7 @@ ### BIOS Directory Table Header -```eval_rst +```{eval-rst} +--------------+---------------+------------------+----------------------------+ | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | +==============+===============+==================+============================+ @@ -281,7 +281,7 @@ ### BIOS Directory Table Entries -```eval_rst +```{eval-rst} +--------------+---------------+------------------+----------------------------+ | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | +==============+===============+==================+============================+ diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md index 684948c..df6c44f 100644 --- a/Documentation/soc/cavium/cn81xx/index.md +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -2,7 +2,7 @@ ## Reference code -```eval_rst +```{eval-rst} The Cavium reference code is called `BDK`_ (board development kit) and is part of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot. ``` @@ -30,7 +30,7 @@ L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed location. It then jumps to the firmware. -```eval_rst +```{eval-rst} For more details have a look at `Cavium CN8XXX Bootflow`_. ``` @@ -46,7 +46,7 @@ ## DRAM setup -```eval_rst +```{eval-rst} The DRAM setup is done by the `BDK`_. ``` @@ -112,7 +112,7 @@ Read the BDK_RNM_CTL_STATUS register at least once after writing it. -```eval_rst +```{eval-rst} .. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK .. _Cavium CN8XXX Bootflow: ../bootflow.html .. _BDK: ../../../vendorcode/cavium/bdk.html diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md index 5ccb47f..ac94be5 100644 --- a/Documentation/soc/cavium/index.md +++ b/Documentation/soc/cavium/index.md @@ -4,5 +4,9 @@ ## Platforms -- [CN81xx series](cn81xx/index.md) -- [CN8xxx bootflow](bootflow.md) +```{toctree} +:maxdepth: 1 + +CN81xx series <cn81xx/index.md> +CN8xxx bootflow <bootflow.md> +``` diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index 1415c72..4d51d67 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -4,7 +4,11 @@ ## Vendor -- [AMD](amd/index.md) -- [Cavium](cavium/index.md) -- [Intel](intel/index.md) -- [Qualcomm](qualcomm/index.md) +```{toctree} +:maxdepth: 1 + +AMD <amd/index.md> +Cavium <cavium/index.md> +Intel <intel/index.md> +Qualcomm <qualcomm/index.md> +``` diff --git a/Documentation/soc/intel/broadwell/index.md b/Documentation/soc/intel/broadwell/index.md index 11a3ce1..0cdd1e7 100644 --- a/Documentation/soc/intel/broadwell/index.md +++ b/Documentation/soc/intel/broadwell/index.md @@ -4,4 +4,8 @@ ## Proprietary blobs -- [mrc.bin and refcode](blobs.md) +```{toctree} +:maxdepth: 1 + +mrc.bin and refcode <blobs.md> +``` diff --git a/Documentation/soc/intel/code_development_model/code_development_model.md b/Documentation/soc/intel/code_development_model/code_development_model.md index 509b8ad..ad27bd4 100644 --- a/Documentation/soc/intel/code_development_model/code_development_model.md +++ b/Documentation/soc/intel/code_development_model/code_development_model.md @@ -58,7 +58,7 @@ SoCs. Here's a table which summarizes common code phase and status: -```eval_rst +```{eval-rst} +----------------+---------------------------------------------+--------------+ | Common code | summary | status | | phase | | | diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index 553fef3..d2629b4 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -17,7 +17,7 @@ Each entry has a *type* that give the other bits in the entry a different meaning. The following types are known: -```eval_rst +```{eval-rst} +-----------+------------------------------------------------------------------+ | no. | Description | +===========+==================================================================+ @@ -56,5 +56,9 @@ ## References -* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Han… -* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents… +```{toctree} +:maxdepth: 1 + +Intel TXT LAB handout <https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf> +FIT BIOS specification <https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bio…> +``` diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index feeb5e9..6d29aca 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -65,23 +65,51 @@ ## Open Source Intel FSP specification -* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp) +```{toctree} +:maxdepth: 1 -* [FSP Specification 1.0](https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf) +About Intel FSP <https://firmware.intel.com/learn/fsp/about-intel-fsp> +``` -* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical… +```{toctree} +:maxdepth: 1 -* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical… +FSP Specification 1.0 <https://www.intel.in/content/dam/www/public/us/en/documents/technical-speci…> +``` -* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786) +```{toctree} +:maxdepth: 1 + +FSP Specification 1.1 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-spec…> +``` + +```{toctree} +:maxdepth: 1 + +FSP Specification 2.0 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-spec…> +``` + +```{toctree} +:maxdepth: 1 + +FSP Specification 2.1 <https://cdrdv2.intel.com/v1/dl/getContent/611786> +``` ## Additional Features in FSP 2.1 specification -- [PPI](ppi/ppi.md) +```{toctree} +:maxdepth: 1 + +PPI <ppi/ppi.md> +``` ## Official bugtracker -- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues) +```{toctree} +:maxdepth: 1 + +IntelFSP/FSP <https://github.com/IntelFsp/FSP/issues> +``` [Issue 10]: https://github.com/IntelFsp/FSP/issues/10 [Issue 13]: https://github.com/IntelFsp/FSP/issues/13 diff --git a/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md b/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md index ab0b513..ce2fb6b 100644 --- a/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md +++ b/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md @@ -43,7 +43,7 @@ ### coreboot to publish EFI_MP_SERVICES_PPI APIs -```eval_rst +```{eval-rst} +------------------------------+------------------------------------------------------------------+ | API | Description | +==============================+==================================================================+ diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md index 6d7afb4..bb14af0 100644 --- a/Documentation/soc/intel/fsp/ppi/ppi.md +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -6,9 +6,17 @@ where FSP should be able to locate PPI, published by boot firmware and able to execute the same in FSP's context. -* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference… +```{toctree} +:maxdepth: 1 + +What is PPI <https://www.intel.com/content/dam/www/public/us/en/documents/reference-guid…> +``` ## List of PPI service ### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU -- [MP Service PPI](mp_service_ppi.md) +```{toctree} +:maxdepth: 1 + +MP Service PPI <mp_service_ppi.md> +``` diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 40d0a56..5eac084 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -4,12 +4,16 @@ ## Platforms -- [Common code development strategy](code_development_model/code_development_model.md) -- [FSP](fsp/index.md) -- [Broadwell](broadwell/index.md) -- [MP Initialization](mp_init/mp_init.md) -- [Microcode Updates](microcode.md) -- [Firmware Interface Table](fit.md) -- [Apollolake](apollolake/index.md) -- [CSE FW Update](cse_fw_update/cse_fw_update.md) -- [Xeon Scalable processor](xeon_sp/index.md) +```{toctree} +:maxdepth: 1 + +Common code development strategy <code_development_model/code_development_model.md> +FSP <fsp/index.md> +Broadwell <broadwell/index.md> +MP Initialization <mp_init/mp_init.md> +Microcode Updates <microcode.md> +Firmware Interface Table <fit.md> +Apollolake <apollolake/index.md> +CSE FW Update <cse_fw_update/cse_fw_update.md> +Xeon Scalable processor <xeon_sp/index.md> +``` diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md index f7776e5..7f21d60 100644 --- a/Documentation/soc/intel/mp_init/mp_init.md +++ b/Documentation/soc/intel/mp_init/mp_init.md @@ -52,5 +52,9 @@ external PPI service feature implemented. ## References -- [PPI](../fsp/ppi/ppi.md) -- [MP Service PPI](../fsp/ppi/mp_service_ppi.md) +```{toctree} +:maxdepth: 1 + +PPI <../fsp/ppi/ppi.md> +MP Service PPI <../fsp/ppi/mp_service_ppi.md> +``` diff --git a/Documentation/soc/intel/xeon_sp/index.md b/Documentation/soc/intel/xeon_sp/index.md index bab09ca..5fe852d 100644 --- a/Documentation/soc/intel/xeon_sp/index.md +++ b/Documentation/soc/intel/xeon_sp/index.md @@ -5,4 +5,8 @@ ## Topics -- [Community preview guide](community_preview_guide.md) +```{toctree} +:maxdepth: 1 + +Community preview guide <community_preview_guide.md> +``` diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index d177c0e..32fac79 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -4,5 +4,9 @@ ## Platforms -- [SC7180 series](sc7180/index.md) -- [SC7280 series](sc7280/index.md) +```{toctree} +:maxdepth: 1 + +SC7180 series <sc7180/index.md> +SC7280 series <sc7280/index.md> +``` diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 81287bb..20bd975 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -4,9 +4,17 @@ ## Nuvoton -- [NPCD378](nuvoton/npcd378.md) -- [NCT5539D](nuvoton/nct5539d.md) +```{toctree} +:maxdepth: 1 + +NPCD378 <nuvoton/npcd378.md> +NCT5539D <nuvoton/nct5539d.md> +``` ## Common -- [PNP devices](common/pnp.md) -- [SSDT generator for generic SuperIOs](common/ssdt.md) +```{toctree} +:maxdepth: 1 + +PNP devices <common/pnp.md> +SSDT generator for generic SuperIOs <common/ssdt.md> +``` diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index 11a0a88..1cc081b 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -8,7 +8,7 @@ ## LDNs -```eval_rst +```{eval-rst} +-------+---------------------------+ | LDN # | Function | +=======+===========================+ @@ -86,7 +86,7 @@ The registers are accessible via IO space and are located at LDN8's IOBASE. -```eval_rst +```{eval-rst} +---------------+-----------------------+ | IOBASE offset | Register | +---------------+-----------------------+ @@ -108,7 +108,7 @@ **Page 1** -```eval_rst +```{eval-rst} +---------------+-----------------------+ | IOBASE offset | Register | +---------------+-----------------------+ diff --git a/Documentation/technotes/asan.md b/Documentation/technotes/asan.md index e0d503a..fedb633 100644 --- a/Documentation/technotes/asan.md +++ b/Documentation/technotes/asan.md @@ -207,7 +207,7 @@ ## Supported platforms Presently, the following architectures support ASan in ramstage: -```eval_rst +```{eval-rst} +------------------+--------------------------------+ | Architecture | Notes | +==================+================================+ @@ -216,7 +216,7 @@ ``` And in romstage ASan is available on the following platforms: -```eval_rst +```{eval-rst} +---------------------+-----------------------------+ | Platform | Notes | +=====================+=============================+ diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md index 52de812..1b022a2 100644 --- a/Documentation/technotes/console.md +++ b/Documentation/technotes/console.md @@ -22,7 +22,7 @@ well. This feature has been tested on the following platforms: -```eval_rst +```{eval-rst} +------------------------------------+ | Tested platforms | +====================================+ @@ -57,10 +57,18 @@ If not we can use other I2C slave devices like an Arduino or a Beagleboard. -* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.or… -* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard… +```{toctree} +:maxdepth: 1 + +Linux I2C Slave interface <https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/…> +BeagleBone Black I2C Slave <https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/…> +``` This feature was added as part of a GSoC 2022 project. Checkout the following blog posts for more details. -* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38… -* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324f… +```{toctree} +:maxdepth: 1 + +coreboot Console via SMBus — Part I <https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273…> +coreboot Console via SMBus — Part II <https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f…> +``` diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index da5b864..e57519f 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -1,8 +1,12 @@ # Technotes -* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) -* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) -* [Unit testing coreboot](2020-03-unit-testing-coreboot.md) -* [Unit Test Code Coverage](2021-05-code-coverage.md) -* [Address Sanitizer](asan.md) -* [coreboot Consoles](console.md) +```{toctree} +:maxdepth: 1 + +Dealing with Untrusted Input in SMM <2017-02-dealing-with-untrusted-input-in-smm.md> +Rebuilding coreboot image generation <2015-11-rebuilding-coreboot-image-generation.md> +Unit testing coreboot <2020-03-unit-testing-coreboot.md> +Unit Test Code Coverage <2021-05-code-coverage.md> +Address Sanitizer <asan.md> +coreboot Consoles <console.md> +``` diff --git a/Documentation/tutorial/flashing_firmware/index.md b/Documentation/tutorial/flashing_firmware/index.md index da3d7f0..3063e4c 100644 --- a/Documentation/tutorial/flashing_firmware/index.md +++ b/Documentation/tutorial/flashing_firmware/index.md @@ -7,10 +7,14 @@ ## Contents -* [Flashing internally](int_flashrom.md) -* [Flashing firmware standalone](ext_standalone.md) -* [Flashing firmware externally supplying direct power](ext_power.md) -* [Flashing firmware externally without supplying direct power](no_ext_power.md) +```{toctree} +:maxdepth: 1 + +Flashing internally <int_flashrom.md> +Flashing firmware standalone <ext_standalone.md> +Flashing firmware externally supplying direct power <ext_power.md> +Flashing firmware externally without supplying direct power <no_ext_power.md> +``` ## General advice @@ -43,7 +47,11 @@ * A UEFI firmware update capsule More details on flashrom's -* [internal programmer](int_flashrom.md) +```{toctree} +:maxdepth: 1 + +internal programmer <int_flashrom.md> +``` ## External method @@ -56,9 +64,13 @@ After exposing the firmware flash IC, read the schematics and use one of the possible methods: -* [Flashing firmware standalone](ext_standalone.md) -* [Flashing firmware externally supplying direct power](ext_power.md) -* [Flashing firmware externally without supplying direct power](no_ext_power.md) +```{toctree} +:maxdepth: 1 + +Flashing firmware standalone <ext_standalone.md> +Flashing firmware externally supplying direct power <ext_power.md> +Flashing firmware externally without supplying direct power <no_ext_power.md> +``` **WARNING:** Using the wrong method or accidentally using the wrong pinout might permanently damage your hardware! diff --git a/Documentation/tutorial/index.md b/Documentation/tutorial/index.md index 384f840..e592370 100644 --- a/Documentation/tutorial/index.md +++ b/Documentation/tutorial/index.md @@ -1,7 +1,11 @@ # Tutorial -* [Part 1: Starting from scratch](part1.md) -* [Part 2: Submitting a patch to coreboot.org](part2.md) -* [Part 3: Writing unit tests](part3.md) -* [Managing local additions](managing_local_additions.md) -* [Flashing firmware](flashing_firmware/index.md) +```{toctree} +:maxdepth: 1 + +Part 1: Starting from scratch <part1.md> +Part 2: Submitting a patch to coreboot.org <part2.md> +Part 3: Writing unit tests <part3.md> +Managing local additions <managing_local_additions.md> +Flashing firmware <flashing_firmware/index.md> +``` diff --git a/Documentation/tutorial/part3.md b/Documentation/tutorial/part3.md index ec49637..377782c 100644 --- a/Documentation/tutorial/part3.md +++ b/Documentation/tutorial/part3.md @@ -28,7 +28,7 @@ test in a particular module. Usually this will be an externally exposed API, which can be used by other modules. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example In case of our UUT, API consist of two methods: @@ -49,7 +49,7 @@ we are expecting from particular functions, when providing particular input parameters. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example .. code-block:: c @@ -71,7 +71,7 @@ dependencies need to be mocked out, since in the user-space host environment, target hardware is not available. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example `i2c_read_field` is calling `i2c_readb`, which eventually invokes @@ -88,7 +88,7 @@ corresponding to UUT. Furthermore, the naming convention is to add the suffix `-test` to the UUT name when creating a new test harness file. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example Considering that UUT is `src/device/i2c.c`, test file should be named @@ -100,7 +100,7 @@ what can be seen under the `src/`. Register a new test in Makefile.mk, by __appending__ test name to the `tests-y` variable. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example .. code-block:: c @@ -114,7 +114,7 @@ test environment. Source files are registered in `<test_name>-srcs` variable. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example .. code-block:: c @@ -128,7 +128,7 @@ tests/<test_dir>/<test_name>` or by running all unit tests (whole suite) for coreboot `make unit-tests`. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example .. code-block:: c @@ -164,7 +164,7 @@ value with an expected value. If the two values do not match, the test fails with an error message. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example In our example, the simplest test is to call UUT for reading our fake @@ -215,7 +215,7 @@ methods. Behind this API, there is usually a simulation of real hardware. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example For purpose of our i2c test, we may introduce two i2c devices with @@ -289,7 +289,7 @@ that the test's implementation of that function is called instead of coreboot's. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example .. code-block:: c @@ -320,7 +320,7 @@ which parameter in which mock should have particular value, or be inside a described range. -```eval_rst +```{eval-rst} .. admonition:: i2c-test example In our example, we may want to check that `platform_i2c_transfer` is @@ -366,7 +366,7 @@ section](https://api.cmocka.org/group__cmocka__mock.html) of the Cmocka API documentation. -```eval_rst +```{eval-rst} .. admonition:: Example There is an non-coreboot example for using Cmocka available @@ -379,7 +379,7 @@ All methods for invoking Cmocka test are described [here](https://api.cmocka.org/group__cmocka__exec.html). -```eval_rst +```{eval-rst} .. admonition:: i2c-test example We don't need any extra setup and teardown functions for i2c-test, so diff --git a/Documentation/util.md b/Documentation/util.md index fe460d9..887d696 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -168,11 +168,15 @@ * __xcompile__ - Cross compile setup `Bash` ## In depth documentation -* [abuild](util/abuild/index.md) -* [cbfstool](util/cbfstool/index.md) -* [ifdtool](util/ifdtool/index.md) -* [intelp2m](util/intelp2m/index.md) -* [smmstoretool](util/smmstoretool/index.md) +```{toctree} +:maxdepth: 1 + +abuild <util/abuild/index.md> +cbfstool <util/cbfstool/index.md> +ifdtool <util/ifdtool/index.md> +intelp2m <util/intelp2m/index.md> +smmstoretool <util/smmstoretool/index.md> +``` ## Generated documentation diff --git a/Documentation/util/cbfstool/index.md b/Documentation/util/cbfstool/index.md index f99b612..917c19d 100644 --- a/Documentation/util/cbfstool/index.md +++ b/Documentation/util/cbfstool/index.md @@ -2,4 +2,8 @@ Contents: -* [Handling memory mapped boot media](mmap_windows.md) +```{toctree} +:maxdepth: 1 + +Handling memory mapped boot media <mmap_windows.md> +``` diff --git a/Documentation/util/ifdtool/index.md b/Documentation/util/ifdtool/index.md index 4348009..c28fd1d 100644 --- a/Documentation/util/ifdtool/index.md +++ b/Documentation/util/ifdtool/index.md @@ -2,5 +2,9 @@ Contents: -* [Intel IFD Binary Extraction](binary_extraction.md) -* [IFD Layout](layout.md) \ No newline at end of file +```{toctree} +:maxdepth: 1 + +Intel IFD Binary Extraction <binary_extraction.md> +IFD Layout <layout.md> +``` diff --git a/Documentation/util/ifdtool/layout.md b/Documentation/util/ifdtool/layout.md index 76c054f..2eb93d3 100644 --- a/Documentation/util/ifdtool/layout.md +++ b/Documentation/util/ifdtool/layout.md @@ -14,7 +14,7 @@ starting with the prefix `SI_` which stands for `silicon initialization` as a way to categorize anything required by the SoC but not provided by coreboot. -```eval_rst +```{eval-rst} +------------+------------------+-----------+-------------------------------------------+ | IFD Region | IFD Region name | FMAP Name | Notes | | index | | | | diff --git a/Documentation/vendorcode/cavium/index.md b/Documentation/vendorcode/cavium/index.md index e06e2ba..ef7481d 100644 --- a/Documentation/vendorcode/cavium/index.md +++ b/Documentation/vendorcode/cavium/index.md @@ -5,4 +5,8 @@ ## Sections -- [BDK](bdk.md) +```{toctree} +:maxdepth: 1 + +BDK <bdk.md> +``` diff --git a/Documentation/vendorcode/eltan/index.md b/Documentation/vendorcode/eltan/index.md index 4484798..015f9f3 100644 --- a/Documentation/vendorcode/eltan/index.md +++ b/Documentation/vendorcode/eltan/index.md @@ -5,4 +5,8 @@ ## Sections -- [Security](security.md) +```{toctree} +:maxdepth: 1 + +Security <security.md> +``` diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md index ffa5ed5..97452e2 100644 --- a/Documentation/vendorcode/index.md +++ b/Documentation/vendorcode/index.md @@ -4,5 +4,9 @@ ## Vendor -- [Cavium](cavium/index.md) -- [Eltan](eltan/index.md) +```{toctree} +:maxdepth: 1 + +Cavium <cavium/index.md> +Eltan <eltan/index.md> +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/73158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804 Gerrit-Change-Number: 73158 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: util/docker: Update Dockerfiles for building documentation
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80312?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/docker: Update Dockerfiles for building documentation ...................................................................... util/docker: Update Dockerfiles for building documentation Update all pip packages related to coreboot's documentation to their latest available version, and update the doc.coreboot.org base image to Alpine 3.19.1. Add myst-parser in preparation to switch from Recommonmark to MyST Parser. TEST: The documentation builds and renders properly when built using the updated container. Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80312 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-jenkins-node/Dockerfile M util/docker/doc.coreboot.org/Dockerfile 2 files changed, 12 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 351cc44..d1a5de9 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -77,12 +77,13 @@ pip3 install --upgrade --no-cache-dir pip && \ pip3 install --no-cache-dir \ setuptools==58.2.0 \ - jinja2==3.1.2 \ + jinja2==3.1.3 \ recommonmark===0.7.1 \ - sphinx===6.2.1 \ + myst-parser===2.0.0 \ + sphinx===7.2.6 \ sphinxcontrib-ditaa===1.0.2 \ - sphinx_autobuild===2021.3.14 \ - sphinx_rtd_theme===1.2.2 \ + sphinx_autobuild===2024.2.4 \ + sphinx_rtd_theme===2.0.0 \ && mkdir -p /home/coreboot/.ssh && \ echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \ chmod 0700 /home/coreboot/.ssh && \ diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index b45660d..d0c32c9 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -1,4 +1,4 @@ -FROM alpine:3.18.3 +FROM alpine:3.19.1 COPY makeSphinx.sh /makeSphinx.sh @@ -13,12 +13,13 @@ echo "source ${VIRTUAL_ENV}/bin/activate" >> /home/coreboot/.bashrc && \ pip3 install --upgrade --no-cache-dir pip && \ pip3 install --no-cache-dir \ - jinja2==3.1.2 \ - recommonmark===0.7.1\ - sphinx===6.2.1 \ + jinja2==3.1.3 \ + recommonmark===0.7.1 \ + myst-parser==2.0.0 \ + sphinx===7.2.6 \ sphinxcontrib-ditaa===1.0.2 \ - sphinx_autobuild===2021.3.14 \ - sphinx_rtd_theme===1.2.2 + sphinx_autobuild===2024.2.4 \ + sphinx_rtd_theme===2.0.0 ADD https://github.com/stathissideris/ditaa/releases/download/v0.11.0/ditaa-0.1… \ /usr/lib/ditaa-0.11.0-standalone.jar -- To view, visit https://review.coreboot.org/c/coreboot/+/80312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Gerrit-Change-Number: 80312 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Maximilian Brune, Patrick Georgi, Philipp Hug, ron minnich. Hello Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81410?usp=email to look at the new patch set (#3). Change subject: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG ...................................................................... arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. Add constants for this new CSR. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 --- M src/arch/riscv/Kconfig M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/payload.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81410/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 Gerrit-Change-Number: 81410 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: docker/doc.coreboot.org: Install pip modules into virtual env
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80311?usp=email ) Change subject: docker/doc.coreboot.org: Install pip modules into virtual env ...................................................................... docker/doc.coreboot.org: Install pip modules into virtual env Currently, pip modules are installed system-wide, which may cause conflicts with modules installed using the package manager. Newer versions of the Alpine base image also mark its system wide Python installation as an externally managed environment, which will cause pip to return an error as per recent Python recommendations [1]. TEST: - `make -C util/docker doc.coreboot.org` builds the container successfully - `make -C util/docker docker-build-docs` builds the documentation successfully [1] https://peps.python.org/pep-0668/ Change-Id: Idd9cc5e6fb28b42ef8e4fa5db01eb9ef192ba0ec Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/docker/doc.coreboot.org/Dockerfile 1 file changed, 11 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index df741d8..b45660d 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -3,15 +3,22 @@ COPY makeSphinx.sh /makeSphinx.sh RUN apk add --no-cache python3 py3-pip make bash git openjdk8-jre ttf-dejavu fontconfig \ - && pip3 install --upgrade --no-cache-dir pip \ - && pip3 install --no-cache-dir \ + && chmod 755 /makeSphinx.sh +RUN adduser -D coreboot + +USER coreboot +ENV VIRTUAL_ENV="/home/coreboot/python3" +ENV PATH=$VIRTUAL_ENV/bin:$PATH:/home/coreboot/.local/bin +RUN python3 -m venv $VIRTUAL_ENV && \ + echo "source ${VIRTUAL_ENV}/bin/activate" >> /home/coreboot/.bashrc && \ + pip3 install --upgrade --no-cache-dir pip && \ + pip3 install --no-cache-dir \ jinja2==3.1.2 \ recommonmark===0.7.1\ sphinx===6.2.1 \ sphinxcontrib-ditaa===1.0.2 \ sphinx_autobuild===2021.3.14 \ - sphinx_rtd_theme===1.2.2 \ - && chmod 755 /makeSphinx.sh + sphinx_rtd_theme===1.2.2 ADD https://github.com/stathissideris/ditaa/releases/download/v0.11.0/ditaa-0.1… \ /usr/lib/ditaa-0.11.0-standalone.jar -- To view, visit https://review.coreboot.org/c/coreboot/+/80311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd9cc5e6fb28b42ef8e4fa5db01eb9ef192ba0ec Gerrit-Change-Number: 80311 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Sean Rhodes. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81395?usp=email ) Change subject: Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Gerrit-Change-Number: 81395 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:10:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Correct the layout
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Sean Rhodes. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81394?usp=email ) Change subject: mb/starlabs/starbook/adl: Correct the layout ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Gerrit-Change-Number: 81394 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:09:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Maximilian Brune, Patrick Georgi, Philipp Hug, ron minnich. Hello Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81410?usp=email to look at the new patch set (#2). Change subject: arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG ...................................................................... arch/riscv: add Kconfig variable RISCV_HAS_MENVCFG Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. Add constants for this new CSR. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 --- M src/arch/riscv/Kconfig M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/payload.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81410/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 Gerrit-Change-Number: 81410 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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