coreboot-gerrit March 2024

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[M] Change in coreboot[main]: arch/riscv: Basic illegal instruction handling
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Philipp Hug. Hello Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#9). Change subject: arch/riscv: Basic illegal instruction handling ...................................................................... arch/riscv: Basic illegal instruction handling Add a simple illegal instruction handler, designed for lowest overhead as opposed to generality. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 73 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 9 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Use fixed BDF for IBL
by Jérémy Compostella (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81321?usp=email ) Change subject: soc/intel/xeon_sp: Use fixed BDF for IBL ...................................................................... Patch Set 8: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81321/comment/fa4cd0f9_ab479570 : PS8, Line 8: In general, I am in favor of using the full name of an acronym the first time it is being used in documentation and I consider that commit message should be documentation level quality. This is not mandatory as I don't know how other feel about that but here are my replacement suggestions. https://review.coreboot.org/c/coreboot/+/81321/comment/46000685_820685ba : PS8, Line 9: IBL codes doesn't support bootloader controlled P2SB hidden and s/IBL/Intermediate Bootloader (IBL)/ https://review.coreboot.org/c/coreboot/+/81321/comment/158cc0bb_d5d208b9 : PS8, Line 10: unhidden. Hence, dyanmically read IBL HPET/IOAPIC BDF by s/BDF/Bus:Device.Function (BDF)/ https://review.coreboot.org/c/coreboot/+/81321/comment/9d378f30_6d135232 : PS8, Line 11: bootloader is not supported, because when P2SB is hidden the s/P2SB/Primary-to-Sideband Bridge (P2SB)/ File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/81321/comment/7bf5df31_3dbee042 : PS8, Line 95: if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { line length limit in coreboot is 96 characters. I don't know why checkpatch did not catch that. Regardless I think the following version is more readable anyway. What do you think ? ``` union p2sb_bdf bdf = { .bus = HPET_BUS_NUM, .dev = HPET_DEV_NUM, .fn = HPET0_FUNC_NUM }; ``` https://review.coreboot.org/c/coreboot/+/81321/comment/57ea2b3d_23471b79 : PS8, Line 105: union p2sb_bdf bdf = {.bus = PCH_IOAPIC_BUS_NUMBER, .dev = PCH_IOAPIC_DEV_NUM, .fn = PCH_IOAPIC_FUNC_NUM}; same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/81321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Gerrit-Change-Number: 81321 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:39:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81410?usp=email ) Change subject: arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: The mistake I made on the first iteration of this was to create a runtime test for the feature. That's a very kernel approach. This is firmware, and you're expected to correctly statically configure for the SOC you're on. So, we expect you to set this variable correctly for the SOC. -- To view, visit https://review.coreboot.org/c/coreboot/+/81410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 Gerrit-Change-Number: 81410 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:21:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: linuxcheck framework which runs from ramstage
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81367?usp=email to look at the new patch set (#5). Change subject: arch/riscv: linuxcheck framework which runs from ramstage ...................................................................... arch/riscv: linuxcheck framework which runs from ramstage Errors in Linux booting are notoriously hard to debug. This change adds a linuxcheck framework that allows testing of things Linux (and other kernels) needs, without having to debug Linux. If LINUXCHECK is set during menuconfig, the linuxcheck function will be called, in S mode, from the ramstage. That function then runs code, in S mode, that tests coreboot M mode code such as SBI. This is extremely handy: because linuxcheck is built into the ramstage, it allows calling any ramstage function, e.g. printk, if required; at the same time, the function is running in S mode, so it is very easy to test SBI calls, instruction emulation, and so on. Note that, if CONFIG_LINUXCHECK is set, the PMPs should enable RWX permissions (instead of R permissions) on the ramstage. For now, until we get the rest of the debugging done, we unconditionally set the permissions. This is a very powerful approach that could also form the core of an SBI fuzzing suite; unlike the currently proposed one, which is based on the KVM fuzzer, this code would not require a Linux kernel to test. It is very light weight. This is also better than the older linuxcheck payload, since it does not need libpayload or seperate compilation. It reduces the testing of SBI and other trap code to its simplest form, and allows to focus on testing SBI, not fighting build systems and large complex kernels. Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/cpu.h A src/arch/riscv/linuxcheck.c M src/arch/riscv/payload.c 5 files changed, 104 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81367/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Gerrit-Change-Number: 81367 Gerrit-PatchSet: 5 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: Basic illegal instruction handling
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Philipp Hug. Hello Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: Basic illegal instruction handling ...................................................................... arch/riscv: Basic illegal instruction handling Add a simple illegal instruction handler, designed for lowest overhead as opposed to generality. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 75 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 8 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Makefile.mk: Enable string-compare command option
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81184?usp=email ) Change subject: Makefile.mk: Enable string-compare command option ...................................................................... Makefile.mk: Enable string-compare command option Change-Id: I7b05b6dd8f1de8689bfcc6825beb728111f6e54a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81184 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Makefile.mk b/Makefile.mk index c901785..bfdb7e3 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -498,6 +498,7 @@ CFLAGS_common += -Wdangling-else -Wmissing-include-dirs CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_common += -Wold-style-declaration # Don't add these GCC specific flags when running scan-build -- To view, visit https://review.coreboot.org/c/coreboot/+/81184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b05b6dd8f1de8689bfcc6825beb728111f6e54a Gerrit-Change-Number: 81184 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: Makefile.mk: Enable string-compare command option
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81184?usp=email ) Change subject: Makefile.mk: Enable string-compare command option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b05b6dd8f1de8689bfcc6825beb728111f6e54a Gerrit-Change-Number: 81184 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:16:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/smmstoretool/fv.c: fix 3 formatting issues
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81173?usp=email ) Change subject: util/smmstoretool/fv.c: fix 3 formatting issues ...................................................................... util/smmstoretool/fv.c: fix 3 formatting issues Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M util/smmstoretool/fv.c 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/util/smmstoretool/fv.c b/util/smmstoretool/fv.c index c9d342e..c6ee913 100644 --- a/util/smmstoretool/fv.c +++ b/util/smmstoretool/fv.c @@ -11,7 +11,7 @@ #include "udk2017.h" // The same as in `smmstore.h` header, which isn't in `commonlib`. -#define SMM_BLOCK_SIZE (64*1024) +#define SMM_BLOCK_SIZE (64 * 1024) static const EFI_GUID EfiVariableGuid = EFI_VARIABLE_GUID; @@ -33,8 +33,7 @@ return checksum; } -bool -fv_init(struct mem_range_t fv) +bool fv_init(struct mem_range_t fv) { if (fv.length % SMM_BLOCK_SIZE != 0) { fprintf(stderr, @@ -152,8 +151,8 @@ return true; } -bool -fv_parse(struct mem_range_t fv, struct mem_range_t *var_store, bool *auth_vars) +bool fv_parse(struct mem_range_t fv, struct mem_range_t *var_store, + bool *auth_vars) { const EFI_FIRMWARE_VOLUME_HEADER *vol_hdr = (void *)fv.start; if (!check_fw_vol_hdr(vol_hdr, fv.length)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b Gerrit-Change-Number: 81173 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: util/smmstoretool/fv.c: fix 3 formatting issues
by Martin L Roth (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Sergii Dmytruk. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81173?usp=email ) Change subject: util/smmstoretool/fv.c: fix 3 formatting issues ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b Gerrit-Change-Number: 81173 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 21 Mar 2024 16:14:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
by ron minnich (Code Review) 21 Mar '24

21 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug. Hello Martin L Roth, Maximilian Brune, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81410?usp=email to look at the new patch set (#4). Change subject: arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG ...................................................................... arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. Add constants for this new CSR. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 --- M src/arch/riscv/Kconfig M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/payload.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81410/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I627dde377708cde2491d4abe625c482d64f7aa87 Gerrit-Change-Number: 81410 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024