coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81313?usp=email ) Change subject: soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4 ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: can we move ahead to submit this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/81313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec Gerrit-Change-Number: 81313 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Mar 2024 11:24:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email ) Change subject: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: can we move ahead to submit this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/81219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Gerrit-Change-Number: 81219 Gerrit-PatchSet: 12 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Mar 2024 11:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81377?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation ...................................................................... soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation Domain SSDT is dyanmically generated by soc_pci_domain_fill_ssdt. SPR has 2 SKUs, XCC and MCC. Dynamic domain SSDT generation could better fit both. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. TEST=intel/archercity CRB Linux ACPI host bridge parsing logs are kept the same before and after, with some minor issue fixed. Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c 9 files changed, 74 insertions(+), 322 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Gerrit-Change-Number: 81377 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain ...................................................................... soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/gnr/soc_acpi.c 3 files changed, 323 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81374?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt ...................................................................... soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt Domain device objects are created with HID/CID/UID. Dynamic domain SSDT generation could benefit the support of SoCs with multiple SKUs, or the case where one set of codes supports multiple SoCs. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/soc_acpi.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81374/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Gerrit-Change-Number: 81374 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Use fixed BDF for IBL
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81321?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Use fixed BDF for IBL ...................................................................... soc/intel/xeon_sp: Use fixed BDF for IBL Integrated Boot Logic (IBL) codes doesn't support bootloader controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden. Hence, dyanmically read IBL HPET/IOAPIC Bus:Device.Function (BDF) by bootloader is not supported, because when P2SB is hidden the register access is denied. Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c 3 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/81321/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Gerrit-Change-Number: 81321 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_acpigen_write_OSC_pci_domain ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81375/comment/b0c96db6_0ebf280a : PS3, Line 175: static void soc_acpigen_OSC_handle_pcie_request(const struct device *domain); > That can be passed as argument: `const bool is_cxl_domain` Done https://review.coreboot.org/c/coreboot/+/81375/comment/5d659d9c_2c967acc : PS3, Line 337: soc_acpigen_OSC_handle_pcie_request > looks like this is not soc specific. Only `get_supported_pci_host_bridge_features` is. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Mar 2024 11:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Shuo Liu (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: Could you please review the updated parts to see if we could close the opens? -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 20 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 22 Mar 2024 11:20:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Attach timestamp around eSOL call
by Subrata Banik (Code Review) 22 Mar '24

22 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81387?usp=email ) Change subject: soc/intel/alderlake: Attach timestamp around eSOL call ...................................................................... soc/intel/alderlake: Attach timestamp around eSOL call This patch adds timestamp start/end entries around the eSOL implementation to track the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246 --- M src/soc/intel/alderlake/romstage/ux.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/81387/1 diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c index af8c783..77439ab 100644 --- a/src/soc/intel/alderlake/romstage/ux.c +++ b/src/soc/intel/alderlake/romstage/ux.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <intelblocks/early_graphics.h> #include <pc80/vga.h> +#include <timestamp.h> #include <ux_locales.h> #include "ux.h" @@ -11,9 +12,13 @@ bool ux_inform_user_of_update_operation(const char *name) { + timestamp_add_now(TS_ESOL_START); + if (!CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) || - !early_graphics_init()) + !early_graphics_init()) { + timestamp_add_now(TS_ESOL_END); return false; + } printk(BIOS_INFO, "Informing user on-display of %s.\n", name); @@ -26,5 +31,6 @@ vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE, (const unsigned char *)text); ux_locales_unmap(); + timestamp_add_now(TS_ESOL_END); return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246 Gerrit-Change-Number: 81387 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: commonlib: Add timestamp entries for eSOL
by Subrata Banik (Code Review) 22 Mar '24

22 Mar '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81386?usp=email ) Change subject: commonlib: Add timestamp entries for eSOL ...................................................................... commonlib: Add timestamp entries for eSOL This patch adds timestamp entries for eSOL (early Sign-Off Life). This is critical to tracking the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81386/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 0ccb3b9..fc7dba8 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -84,6 +84,8 @@ TS_COPYVPD_RW_END = 552, TS_TPM_ENABLE_UPDATE_START = 553, TS_TPM_ENABLE_UPDATE_END = 554, + TS_ESOL_START = 555, + TS_ESOL_END = 556, /* 900-940 reserved for vendorcode extensions (900-940: AMD) */ TS_AGESA_INIT_RESET_START = 900, @@ -265,6 +267,8 @@ TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END, "started TPM enable update"), TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"), + TS_NAME_DEF(TS_ESOL_START, 0, "started early sign-off life (eSOL) notification"), + TS_NAME_DEF(TS_ESOL_END, 0, "finished early sign-off life (eSOL) notification"), /* AMD related timestamps */ TS_NAME_DEF(TS_AGESA_INIT_RESET_START, TS_AGESA_INIT_RESET_END, "calling AmdInitReset"), -- To view, visit https://review.coreboot.org/c/coreboot/+/81386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb Gerrit-Change-Number: 81386 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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