Leah Rowe has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80716?usp=email )
Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
Normally, this is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is present. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80716/1
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6e6948b..6e0ccf3 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -461,12 +461,21 @@
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
+static void gma_func0_disable(struct device *dev)
+{
+ /* Disable VGA decode */
+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
+
+ dev->enabled = 0;
+}
+
static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.acpi_fill_ssdt = gma_generate_ssdt,
+ .vga_disable = gma_func0_disable,
.ops_pci = &pci_dev_ops_pci,
};
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80663/comment/75e90c05_6ed5f19c :
PS3, Line 28: screebo
Karis?
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Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
Patch Set 3: Code-Review+2
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Change subject: include/device/azalia_device.h: Fix incorrect bit shift
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80727/comment/494b0ffe_0c500724 :
PS2, Line 9: TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
: same binary.
Only one board uses this in the tree (mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c) and this won't be true...
OTOH this patch is indeed correct.
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Hello Crystal Guo, Hung-Te Lin, Xi Chen, Xixi Chen, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptive
......................................................................
soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptive
Starting from MT8195, MediaTek platform supports "dram adaptive" to
automatically detect dram information, including channel, rank, die
size..., and can automatically configure EMI settings. So we can just
pass a placeholder param blob to `mt_mem_init_run` by enabling this
option.
Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
need to implement `get_sdram_config` to get onboard DRAM configuration
info.
TEST=emerge-geralt coreboot && emerge-asurada coreboot
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada
Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/mainboard/google/cherry/Makefile.mk
D src/mainboard/google/cherry/sdram_configs.c
M src/mainboard/google/corsola/Makefile.mk
D src/mainboard/google/corsola/sdram_configs.c
M src/mainboard/google/geralt/Makefile.mk
D src/mainboard/google/geralt/sdram_configs.c
M src/soc/mediatek/common/Kconfig
M src/soc/mediatek/common/include/soc/dramc_param_common.h
M src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8186/include/soc/dramc_param.h
M src/soc/mediatek/mt8188/include/soc/dramc_param.h
M src/soc/mediatek/mt8192/include/soc/dramc_param.h
M src/soc/mediatek/mt8195/include/soc/dramc_param.h
13 files changed, 24 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/80687/4
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Change subject: superio/ite: Add IT8629E
......................................................................
Patch Set 11: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add memory type check utils
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/util.c:
https://review.coreboot.org/c/coreboot/+/80632/comment/4179d5b1_e95195f7 :
PS3, Line 126: __weak bool is_memtype_processor_attached(UINT16 mem_type)
: {
: return true;
: }
:
> For this case, if we only inline but not add static, the optimization out will not happen. However, if we define static, we need to do this in header file which is not straightforward to support overrides unless a corresponding Kconfig is used.
>
CONFIG_SOC_INTEL_HAS_CXL ?
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