Attention is currently required from: Martin L Roth.
Hello Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80732?usp=email
to look at the new patch set (#2).
Change subject: util/crossgcc: Also build LLVM LD
......................................................................
util/crossgcc: Also build LLVM LD
When doing LTO the clang linker frontend needs to use LLD or gold. Build
LLD as that is the configuration that is best tested.
Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/crossgcc/buildgcc
A util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum
3 files changed, 15 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/80732/2
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80730?usp=email )
Change subject: util/xcompile: Use a more complete clang target
......................................................................
util/xcompile: Use a more complete clang target
When the compilers is used as a linker frontend clang tries to match the
target string with what it supports internally. If it's not sufficiently
complete it will forward linking to GCC which is not desirable. This is
necessary when doing LTO with clang.
Change-Id: Ie9356a2bc0f5b77e934cc16482d6ccb1961195dc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/xcompile/xcompile
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/80730/1
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 1eecc7e..989b4b7 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -462,7 +462,7 @@
for clang_arch in $TCLIST invalid; do
for clang_prefix in $search $XGCCPATH "$GENERIC_COMPILER_PREFIX"; do
- testcc "${clang_prefix}clang" "-target ${clang_arch}-$TABI -c" && break 2
+ testcc "${clang_prefix}clang" "-target ${clang_arch}-none-unknown-${TABI} -c" && break 2
done
done
@@ -471,7 +471,7 @@
# but that's more of a clang limitation. Let's be optimistic
# that this will change in the future.
CLANG="${clang_prefix}clang"
- CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG"
+ CFLAGS_CLANG="-target ${clang_arch}-none-unknown-${TABI} $CFLAGS_CLANG"
fi
}
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80663/comment/c5396eb0_456b2bdc :
PS4, Line 9: Improve SSD readiness time by enabling earlier power sequencing.
What are the old and new timings?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80727?usp=email )
Change subject: include/device/azalia_device.h: Fix incorrect bit shift
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80727/comment/367c09a8_8f401c3d :
PS2, Line 7: Fix incorrect bit shift
Maybe more specific:
> Shift location2 by 28 bits
https://review.coreboot.org/c/coreboot/+/80727/comment/76a3129b_b56c7662 :
PS2, Line 8:
Please mention the source, that this is the correct value.
Patchset:
PS2:
Thank you for finding this.
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Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/braswell/gpio.c:
https://review.coreboot.org/c/coreboot/+/80193/comment/b28e94ca_89e888a9 :
PS1, Line 222: (
oh, there are even more superfluous parenthesis in this patch. won't comment on all of them, but would be good if you can rework the patch and remove those
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Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> I think as long as U-Boot still has it (https://github. […]
the x86 socs mainly use integers for mmio addresses while the arm socs mainly use pointers for mmio addresses, so keeping both and using what's suited best is probably the way to go. mainly working on x86, i hoped that the result of looking into things would be that we'll only need the functions that take an integer, but the arm soc code mainly uses pointers, and i'd say both have good reasons to do things the way they do. since the topic was discussed and i gathered some data on it, i'd say that i could just mark this one as resolved, but leaving it as still unresolved for maybe a day or so to give the others a chance to comment
File src/soc/intel/denverton_ns/acpi.c:
https://review.coreboot.org/c/coreboot/+/80193/comment/5a414d8c_7b2736dc :
PS1, Line 172: (
second pair of parenthesis aren't needed
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