Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80415?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings glinda in line with cezanne, mendocino,
phoenix and picasso. This also prepares glinda to use the common
function gpp_clk_setup_common.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415
Reviewed-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/chip.h
M src/soc/amd/glinda/fch.c
3 files changed, 7 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Anand Vaikar: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a042ea2..8a6649a 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -75,6 +75,7 @@
select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h
index d33261f..085bac5 100644
--- a/src/soc/amd/glinda/chip.h
+++ b/src/soc/amd/glinda/chip.h
@@ -7,6 +7,7 @@
#include <amdblocks/chip.h>
#include <amdblocks/i2c.h>
+#include <amdblocks/pci_clk_req.h>
#include <gpio.h>
#include <soc/i2c.h>
#include <soc/southbridge.h>
@@ -92,11 +93,7 @@
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */
- enum {
- GPP_CLK_ON, /* GPP clock always on; default */
- GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
- GPP_CLK_OFF, /* GPP clk off */
- } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
+ enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
/* performance policy for the PCIe links: power consumption vs. link speed */
enum {
diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index 93597c9..bb03ad4 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -6,6 +6,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/gpio.h>
+#include <amdblocks/pci_clk_req.h>
#include <amdblocks/reset.h>
#include <amdblocks/smi.h>
#include <assert.h>
@@ -130,7 +131,7 @@
/* configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void)
{
- const struct soc_amd_glinda_config *cfg = config_of_soc();
+ struct soc_amd_glinda_config *cfg = config_of_soc();
/* look-up table to be able to iterate over the PCIe clock output settings */
const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
@@ -145,6 +146,8 @@
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
+ ARRAY_SIZE(cfg->gpp_clk_config));
for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
/*
--
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Change subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80665?usp=email )
Change subject: soc/intel/adl: Set slp-s0 counter frequency
......................................................................
soc/intel/adl: Set slp-s0 counter frequency
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time
Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
Sukumar Ghorai: Looks good to me, but someone else must approve
Subrata Banik: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index b81bfdd..2d42cad 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -549,4 +549,9 @@
config HAVE_BMP_LOGO_COMPRESS_LZMA
default n
+config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
+ default 0x2005
+ help
+ slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz).
+
endif
--
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80727?usp=email )
Change subject: include/device/azalia_device.h: Fix incorrect bit shift
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80727/comment/4193fd62_29750923 :
PS2, Line 9: TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
: same binary.
> The connected pins have these values:
> ```
> 0x12 0x9fa60130
> 0x14 0x9e170110
> 0x15 0x04211020
> 0x1a 0x04a1113c
> 0x1d 0x88f70145
> ```
>
> These values decoded would turn into:
> ```
> AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
> INTEGRATED,
> INTERNAL,
> 0xf,
> MIC_IN,
> OTHER_DIGITAL,
> COLOR_UNKNOWN,
> NO_JACK_PRESENCE_DETECT,
> 0x3,
> 0x0
> )),
> AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
> INTEGRATED,
> INTERNAL,
> 0xe,
> SPEAKER,
> OTHER_ANALOG,
> COLOR_UNKNOWN,
> NO_JACK_PRESENCE_DETECT,
> 0x1,
> 0x0
> )),
> AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
> JACK,
> EXTERNAL_PRIMARY_CHASSIS,
> RIGHT,
> HP_OUT,
> STEREO_MONO_1_8,
> BLACK,
> JACK_PRESENCE_DETECT,
> 0x2,
> 0x0
> )),
> AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
> JACK,
> EXTERNAL_PRIMARY_CHASSIS,
> RIGHT,
> MIC_IN,
> STEREO_MONO_1_8,
> BLACK,
> NO_JACK_PRESENCE_DETECT,
> 0x3,
> 0xc
> )),
> AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC(
> INTEGRATED,
> EXTERNAL_PRIMARY_CHASSIS,
> SPECIAL8,
> DEVICE_OTHER,
> OTHER_ANALOG,
> COLOR_UNKNOWN,
> NO_JACK_PRESENCE_DETECT,
> 0x4,
> 0x5
> )),
> ```
> Using this would produce the same binary with timeless builds. However, I find it very odd to be using values like '0xf' and '0xe' in `location_1` as they are reserved values.
>
> I don't think we have to change any of the enums in this case. My assumption is the author assumed `AZALIA_PIN_DESC()` was correct and used the enums that made sense. However, I also understand that it may be better to just keep the tested values even if they are incorrect. I'll leave that decision to you.
Fair enough. Let's wait a few days for the author to respond and then let's go ahead with not changing it. You might want to update the commit message though to indicate that this changes things for that particular board.
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Change subject: include/device/azalia_device.h: Fix incorrect bit shift
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80727/comment/aa61ff88_f00bda48 :
PS2, Line 9: TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
: same binary.
> Only one board uses this in the tree (mainboard/clevo/tgl-u/variants/l140mu/hda_verb. […]
The connected pins have these values:
```
0x12 0x9fa60130
0x14 0x9e170110
0x15 0x04211020
0x1a 0x04a1113c
0x1d 0x88f70145
```
These values decoded would turn into:
```
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
INTEGRATED,
INTERNAL,
0xf,
MIC_IN,
OTHER_DIGITAL,
COLOR_UNKNOWN,
NO_JACK_PRESENCE_DETECT,
0x3,
0x0
)),
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
INTEGRATED,
INTERNAL,
0xe,
SPEAKER,
OTHER_ANALOG,
COLOR_UNKNOWN,
NO_JACK_PRESENCE_DETECT,
0x1,
0x0
)),
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
JACK,
EXTERNAL_PRIMARY_CHASSIS,
RIGHT,
HP_OUT,
STEREO_MONO_1_8,
BLACK,
JACK_PRESENCE_DETECT,
0x2,
0x0
)),
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
JACK,
EXTERNAL_PRIMARY_CHASSIS,
RIGHT,
MIC_IN,
STEREO_MONO_1_8,
BLACK,
NO_JACK_PRESENCE_DETECT,
0x3,
0xc
)),
AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC(
INTEGRATED,
EXTERNAL_PRIMARY_CHASSIS,
SPECIAL8,
DEVICE_OTHER,
OTHER_ANALOG,
COLOR_UNKNOWN,
NO_JACK_PRESENCE_DETECT,
0x4,
0x5
)),
```
Using this would produce the same binary with timeless builds. However, I find it very odd to be using values like '0xf' and '0xe' in `location_1` as they are reserved values.
I don't think we have to change any of the enums in this case. My assumption is the author assumed `AZALIA_PIN_DESC()` was correct and used the enums that made sense. However, I also understand that it may be better to just keep the tested values even if they are incorrect. I'll leave that decision to you.
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Hello Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80717?usp=email
to look at the new patch set (#2).
Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/80717/2
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Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
Abandoned
accidentally used master branch. see 80717 instead which pushes to main.
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Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/80717/1
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6e6948b..6e0ccf3 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -461,12 +461,21 @@
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
+static void gma_func0_disable(struct device *dev)
+{
+ /* Disable VGA decode */
+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
+
+ dev->enabled = 0;
+}
+
static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.acpi_fill_ssdt = gma_generate_ssdt,
+ .vga_disable = gma_func0_disable,
.ops_pci = &pci_dev_ops_pci,
};
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80716?usp=email
to look at the new patch set (#2).
Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is present. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80716/2
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