Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email )
Change subject: vc/google/chromeos: Refactor bmp_logo_filename() for product segment
......................................................................
vc/google/chromeos: Refactor bmp_logo_filename() for product segment
* Differentiate boot splash logos for Chromebook, Chromebook-Plus
(hard-branded), and Chromebook-Plus (soft-branded) devices.
* Logic depends on hardware compliance and VPD product requirements.
BUG=b:324107408
TEST=Verified logo selection based on compliance and product
requirements.
Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/vendorcode/google/chromeos/Makefile.mk
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/splash.c
M src/vendorcode/google/chromeos/tpm_factory_config.c
A src/vendorcode/google/chromeos/vpd_device_feature.c
5 files changed, 91 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/80738/1
diff --git a/src/vendorcode/google/chromeos/Makefile.mk b/src/vendorcode/google/chromeos/Makefile.mk
index af37a09..1ff1e18 100644
--- a/src/vendorcode/google/chromeos/Makefile.mk
+++ b/src/vendorcode/google/chromeos/Makefile.mk
@@ -10,6 +10,7 @@
ramstage-$(CONFIG_USE_SAR) += sar.c
ramstage-$(CONFIG_TPM_GOOGLE) += cr50_enable_update.c
ramstage-$(CONFIG_TPM_GOOGLE) += tpm_factory_config.c
+ramstage-$(CONFIG_VPD) += vpd_device_feature.c
romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index a4315c3..7689a2f 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -43,9 +43,25 @@
* - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus
* hardware specifications.
*
- * To be considered a Chromebook Plus, either of these conditions needs to be met.
+ * To be considered a Chromebook Plus, both of these conditions needs to be met.
*/
-bool chromeos_device_branded_plus(void);
+bool chromeos_device_branded_plus_hard(void);
+
+/*
+ * Determines whether a ChromeOS device is soft-branded as a Chromebook Plus
+ * after meeting below conditions:
+ *
+ * - Device is compliant to the Chromebook-Plus Hardware Specification.
+ * - Business decision makes this device qualified as Chromebook-Plus.
+ *
+ * To be considered a soft-branded Chromebook Plus, both of these conditions needs to be met.
+ */
+bool chromeos_device_branded_plus_soft(void);
+
+/*
+ * Return the value after reading the VPD key named "feature_device_info".
+ */
+const char *chromeos_get_feature_device_info(void);
/*
* Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c
index 3532fb8..f63f526 100644
--- a/src/vendorcode/google/chromeos/splash.c
+++ b/src/vendorcode/google/chromeos/splash.c
@@ -5,7 +5,9 @@
const char *bmp_logo_filename(void)
{
- if (chromeos_device_branded_plus())
+ if (chromeos_device_branded_plus_hard())
+ return "cb_plus_logo.bmp";
+ else if (chromeos_device_branded_plus_soft())
return "cb_plus_logo.bmp";
else
return "cb_logo.bmp";
diff --git a/src/vendorcode/google/chromeos/tpm_factory_config.c b/src/vendorcode/google/chromeos/tpm_factory_config.c
index 44fb9f0..4c17d69 100644
--- a/src/vendorcode/google/chromeos/tpm_factory_config.c
+++ b/src/vendorcode/google/chromeos/tpm_factory_config.c
@@ -3,12 +3,13 @@
#include <assert.h>
#include <console/console.h>
#include <security/tpm/tss.h>
+#include <string.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define CHROMEBOOK_PLUS_HARD_BRANDED BIT(4)
-#define CHROMEBOOK_PLUS_SOFT_BRANDED BIT(0)
-#define CHROMEBOOK_PLUS_DEVICE (CHROMEBOOK_PLUS_HARD_BRANDED | CHROMEBOOK_PLUS_SOFT_BRANDED)
+#define CHROMEBOOK_PLUS_HW_COMPLIANCE BIT(0)
+#define CHROMEBOOK_PLUS_DEVICE (CHROMEBOOK_PLUS_HARD_BRANDED & CHROMEBOOK_PLUS_HW_COMPLIANCE)
uint64_t chromeos_get_factory_config(void)
{
@@ -47,9 +48,9 @@
* - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus
* hardware specifications.
*
- * To be considered a Chromebook Plus, either of these conditions needs to be met.
+ * To be considered a hard-branded Chromebook Plus, both of these conditions needs to be met.
*/
-bool chromeos_device_branded_plus(void)
+bool chromeos_device_branded_plus_hard(void)
{
uint64_t factory_config = chromeos_get_factory_config();
@@ -58,3 +59,51 @@
return factory_config & CHROMEBOOK_PLUS_DEVICE;
}
+
+/*
+ * Determines whether a ChromeOS device is compliant to the Chromebook Plus
+ * hardware specific:
+ *
+ * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus
+ * hardware specifications.
+ *
+ * A ChromeOS device that compliant to the Chromebook Plus hardware specification
+ * (but don't have "chromebook-plus" branding on the chassis) can be often branded
+ * as "Regular Chromebook" or "Soft-branded Chromebook-Plus" depending on the product
+ * requirement.
+ */
+static bool chromeos_device_plus_hw_compliant(void)
+{
+ uint64_t factory_config = chromeos_get_factory_config();
+
+ if (factory_config == UNDEFINED_FACTORY_CONFIG)
+ return false;
+
+ return factory_config & CHROMEBOOK_PLUS_HW_COMPLIANCE;
+}
+
+/*
+ * Determines whether a ChromeOS device is soft-branded as a Chromebook Plus
+ * after meeting below conditions:
+ *
+ * - Device is compliant to the Chromebook-Plus Hardware Specification.
+ * - Product requirement makes this device qualified as Chromebook-Plus.
+ *
+ * To be considered a soft-branded Chromebook Plus, both of these conditions needs to be met.
+ */
+bool chromeos_device_branded_plus_soft(void)
+{
+ if (!chromeos_device_plus_hw_compliant())
+ return false;
+
+ const char *device_info = chromeos_get_feature_device_info();
+
+ /*
+ * Feature level: First 3 character from `feature_device_info` VPD
+ * If `Feature level` = 'CAI` then chromebook-plus.
+ */
+ if (strncmp((char *)device_info, "CAI", 3) == 0)
+ return true;
+ else
+ return false;
+}
diff --git a/src/vendorcode/google/chromeos/vpd_device_feature.c b/src/vendorcode/google/chromeos/vpd_device_feature.c
new file mode 100644
index 0000000..8ecbf56
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vpd_device_feature.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/vpd/vpd.h>
+#include <drivers/vpd/vpd_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define VPD_KEY_FEATURE_DEVICE_INFO "feature_device_info"
+#define VPD_DEVICE_INFO_LEN 64
+
+const char *chromeos_get_feature_device_info(void)
+{
+ static char device_info[VPD_DEVICE_INFO_LEN];
+ if (vpd_gets(VPD_KEY_FEATURE_DEVICE_INFO, device_info, VPD_DEVICE_INFO_LEN, VPD_RW))
+ return device_info;
+ return "";
+}
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80727?usp=email )
Change subject: include/device/azalia_device.h: Correct location2 shift to 28 bits
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80727/comment/41cee239_b0b39d28 :
PS2, Line 9: TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
: same binary.
> btw. this now also explains some weird values from the vendor... […]
I saw your other change CB:80695, where you already worked on this board as well. I would suggest doing it that way:
- get CB:80727 (this one) merged, but add a note in the commit message that this actually corrects the resulting values for L140MU
- get CB:80695 merged
- CB:80720 fixes the wrong vendor value comments
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Change subject: mb/clevo/tgl-u: hda_verbs: correct vendor value comments
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: include/device: Merge enums from azalia_device.h and azalia.h
......................................................................
Patch Set 3:
(3 comments)
File src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/80695/comment/b561281d_421e4982 :
PS3, Line 16: AZALIA_SEPARATE_CHASSIS
bad decoding when porting the board; vendor: INTERNAL; I will fix this in a follow-up change
https://review.coreboot.org/c/coreboot/+/80695/comment/faf5e8ce_8b59b0ab :
PS3, Line 27: AZALIA_SEPARATE_CHASSIS
bad decoding when porting the board; vendor: INTERNAL; I will fix this in a follow-up change
https://review.coreboot.org/c/coreboot/+/80695/comment/ab70414a_87c00a0d :
PS3, Line 38: vendor
should have been linux; I will fix this in a follow-up change
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Change subject: include/device: Merge enums from azalia_device.h and azalia.h
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80695/comment/b9da0f7c_9d7a1b87 :
PS3, Line 16: - Locations are now expressed using a combination of ORs (e.g.
: `AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT`).
:
This should be a separate change
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Change subject: include/device: Merge enums from azalia_device.h and azalia.h
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80695/comment/5ffd9520_0a4baf8c :
PS3, Line 15: - All enum names now use the `AZALIA_` prefix.
what for? I would rather remove it
Patchset:
PS3:
Thank you for cleaning that up!
File src/include/device/azalia_device.h:
https://review.coreboot.org/c/coreboot/+/80695/comment/2b962719_d4910f21 :
PS3, Line 85: = 0x2,
It's a enum, do we really want to have explicit values here?
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Change subject: soc/amd/common/acpi/upep: Fix UUID conditional and add notifications required for Windows Modern Standby notifications
......................................................................
Patch Set 4:
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Commit Message:
https://review.coreboot.org/c/coreboot/+/77742/comment/157dd802_b750c16f :
PS4, Line 6:
> `Possible long commit subject (prefer a maximum 65 characters)`
Please fix. Maybe split it into two patches?
Patchset:
PS4:
It’d be great to get these in?
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Change subject: soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASL
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80719/comment/e1d9d3be_22831f90 :
PS1, Line 9: Backport
By the way, why “backport” and not just “port”?
https://review.coreboot.org/c/coreboot/+/80719/comment/f17cbb82_116ecb4b :
PS1, Line 14: Verify TCSS XHCI power management
: working
How can this be tested?
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Change subject: soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80718/comment/fbd8e20e_095433e1 :
PS1, Line 9: Backport 9c348a7b7ea3422a74af9b820275751e9abb4a12 from Alder Lake to
> `Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug unplug of TBT device")'`
Please fix.
https://review.coreboot.org/c/coreboot/+/80718/comment/d1735f4a_ac9aa8dd :
PS1, Line 10: fix a similar issue present on Tiger Lake
Please add a dot/period at the end of sentences.
https://review.coreboot.org/c/coreboot/+/80718/comment/ab3c73f7_00eb323f :
PS1, Line 11:
It’d be great if you copied the other commit message to ease review.
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