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[XS] Change in coreboot[main]: mb/clevo/tgl-u: hda_verbs: correct vendor value comments
by Nicholas Sudsgaard (Code Review) 25 Feb '24

25 Feb '24

Attention is currently required from: Arthur Heymans, Michael Niewöhner. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80720?usp=email ) Change subject: mb/clevo/tgl-u: hda_verbs: correct vendor value comments ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Rebase this on top of CB:80740. -- To view, visit https://review.coreboot.org/c/coreboot/+/80720?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45b1d09d5a11b357ac2a20ef448ea642540cdc99 Gerrit-Change-Number: 80720 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 25 Feb 2024 01:32:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: include/device/azalia_device.h: Merge location1 and location2
by Nicholas Sudsgaard (Code Review) 25 Feb '24

25 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80740?usp=email ) Change subject: include/device/azalia_device.h: Merge location1 and location2 ...................................................................... include/device/azalia_device.h: Merge location1 and location2 This changes the location to be expressed as a combination of ORs. This allows aliases for special locations. For example, `AZALIA_REAR_PANEL` is easier to read than `AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`. Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/include/device/azalia_device.h M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c M src/mainboard/siemens/chili/variants/chili/hda_verb.c 3 files changed, 32 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/80740/1 diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 89057de..addecf3 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -50,10 +50,10 @@ }; enum azalia_pin_location_gross { - AZALIA_EXTERNAL_PRIMARY_CHASSIS = 0x0, - AZALIA_INTERNAL = 0x1, - AZALIA_SEPARATE_CHASSIS = 0x2, - AZALIA_LOCATION_OTHER = 0x3, + AZALIA_EXTERNAL_PRIMARY_CHASSIS = 0x00, + AZALIA_INTERNAL = 0x10, + AZALIA_SEPARATE_CHASSIS = 0x20, + AZALIA_LOCATION_OTHER = 0x30, }; enum azalia_pin_location_geometric { @@ -69,6 +69,16 @@ AZALIA_SPECIAL9 = 0x9, }; +enum azalia_pin_location_special { + AZALIA_REAR_PANEL = AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_SPECIAL7, + AZALIA_DRIVE_BAY = AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_SPECIAL8, + AZALIA_RISER = AZALIA_INTERNAL | AZALIA_SPECIAL7, + AZALIA_DIGITAL_DISPLAY = AZALIA_INTERNAL | AZALIA_SPECIAL8, + AZALIA_ATAPI = AZALIA_INTERNAL | AZALIA_SPECIAL9, + AZALIA_MOBILE_LID_INSIDE = AZALIA_LOCATION_OTHER | AZALIA_SPECIAL7, + AZALIA_MOBILE_LID_OUTSIDE = AZALIA_LOCATION_OTHER | AZALIA_SPECIAL8, +}; + enum azalia_pin_device { AZALIA_LINE_OUT = 0x0, AZALIA_SPEAKER = 0x1, @@ -123,16 +133,14 @@ AZALIA_NO_JACK_PRESENCE_DETECT = 0x1, }; -#define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, misc, \ - association, sequence) \ - ((((conn) << 30) & 0xc0000000) | \ - (((location2) << 28) & 0x30000000) | \ - (((location1) << 24) & 0x0f000000) | \ - (((dev) << 20) & 0x00f00000) | \ - (((type) << 16) & 0x000f0000) | \ - (((color) << 12) & 0x0000f000) | \ - (((misc) << 8) & 0x00000f00) | \ - (((association) << 4) & 0x000000f0) | \ +#define AZALIA_PIN_DESC(conn, location, dev, type, color, misc, association, sequence) \ + ((((conn) << 30) & 0xc0000000) | \ + (((location) << 24) & 0x3f000000) | \ + (((dev) << 20) & 0x00f00000) | \ + (((type) << 16) & 0x000f0000) | \ + (((color) << 12) & 0x0000f000) | \ + (((misc) << 8) & 0x00000f00) | \ + (((association) << 4) & 0x000000f0) | \ (((sequence) << 0) & 0x0000000f)) #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c index 3614a07..db9da04 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -13,8 +13,7 @@ /* Microphone (display lid), vendor value: 0x90a60130 */ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( AZALIA_INTEGRATED, - AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ - AZALIA_SPECIAL7, /* lid, vendor: AZALIA_LOCATION_UNKNOWN */ + AZALIA_MOBILE_LID_INSIDE, /* vendor: AZALIA_SEPARATE_CHASSIS */ AZALIA_MIC_IN, AZALIA_OTHER_DIGITAL, AZALIA_COLOR_UNKNOWN, @@ -25,8 +24,7 @@ /* Integrated speakers, vendor value: 0x90170110 */ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( AZALIA_INTEGRATED, - AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ - AZALIA_BOTTOM, /* vendor: AZALIA_LOCATION_UNKNOWN */ + AZALIA_LOCATION_OTHER | AZALIA_BOTTOM, /* vendor: AZALIA_SEPARATE_CHASSIS */ AZALIA_SPEAKER, AZALIA_OTHER_ANALOG, AZALIA_COLOR_UNKNOWN, @@ -37,8 +35,8 @@ /* Headphones, vendor value: 0x02211020 */ AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( AZALIA_JACK, - AZALIA_EXTERNAL_PRIMARY_CHASSIS, - AZALIA_RIGHT, /* vendor: AZALIA_FRONT */ + /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT */ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, AZALIA_HP_OUT, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK, @@ -49,8 +47,8 @@ /* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( AZALIA_JACK, - AZALIA_EXTERNAL_PRIMARY_CHASSIS, - AZALIA_RIGHT, /* vendor: AZALIA_REAR */ + /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR */ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, AZALIA_MIC_IN, AZALIA_STEREO_MONO_1_8, AZALIA_BLACK, /* vendor: AZALIA_PINK */ @@ -61,8 +59,7 @@ /* PCBEEP, vendor value: 0x41748245 */ AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC( AZALIA_INTEGRATED, /* vendor: AZALIA_NC */ - AZALIA_INTERNAL, /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS */ - AZALIA_LOCATION_UNKNOWN, /* vendor: AZALIA_REAR */ + AZALIA_INTERNAL, /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR */ AZALIA_DEVICE_OTHER, /* vendor: AZALIA_MODEM_HANDSET_SIDE */ AZALIA_OTHER_ANALOG, /* vendor: AZALIA_RCA */ AZALIA_COLOR_UNKNOWN, /* vendor: AZALIA_PURPLE */ diff --git a/src/mainboard/siemens/chili/variants/chili/hda_verb.c b/src/mainboard/siemens/chili/variants/chili/hda_verb.c index 5846469..c55ed0a 100644 --- a/src/mainboard/siemens/chili/variants/chili/hda_verb.c +++ b/src/mainboard/siemens/chili/variants/chili/hda_verb.c @@ -17,7 +17,6 @@ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( /* 0x14 Speaker OUT */ AZALIA_INTEGRATED, AZALIA_INTERNAL, - AZALIA_LOCATION_UNKNOWN, AZALIA_SPEAKER, AZALIA_OTHER_ANALOG, AZALIA_COLOR_UNKNOWN, @@ -27,8 +26,7 @@ )), AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( /* 0x21 Headphone OUT */ AZALIA_JACK, - AZALIA_EXTERNAL_PRIMARY_CHASSIS, - AZALIA_FRONT, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, AZALIA_HP_OUT, AZALIA_COMBINATION, AZALIA_BLACK, @@ -38,8 +36,7 @@ )), AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( /* 0x19 MIC2 */ AZALIA_JACK, - AZALIA_EXTERNAL_PRIMARY_CHASSIS, - AZALIA_FRONT, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, AZALIA_MIC_IN, AZALIA_COMBINATION, AZALIA_BLACK, @@ -70,8 +67,7 @@ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_CFG_NC(1)), AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( AZALIA_JACK, - AZALIA_EXTERNAL_PRIMARY_CHASSIS, - AZALIA_SPECIAL7, + AZALIA_REAR_PANEL, AZALIA_DIGITAL_OTHER_OUT, AZALIA_OTHER_DIGITAL, AZALIA_COLOR_UNKNOWN, -- To view, visit https://review.coreboot.org/c/coreboot/+/80740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Gerrit-Change-Number: 80740 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/clevo/tgl-u: hda_verbs: correct vendor value comments
by Nicholas Sudsgaard (Code Review) 25 Feb '24

25 Feb '24

Attention is currently required from: Arthur Heymans, Michael Niewöhner. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80720?usp=email ) Change subject: mb/clevo/tgl-u: hda_verbs: correct vendor value comments ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Just my 2 cents, maybe the `/* vendor/linux: AZALIA_... */` comments are superfluous. As long as you provide the vendor values (which you do) you can decode these using the hda-decoder I wrote relatively easily. File src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c: https://review.coreboot.org/c/coreboot/+/80720/comment/c58b3b6c_c00f6d0c : PS1, Line 54: vendor linux. -- To view, visit https://review.coreboot.org/c/coreboot/+/80720?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45b1d09d5a11b357ac2a20ef448ea642540cdc99 Gerrit-Change-Number: 80720 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 25 Feb 2024 00:20:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
by Felix Singer (Code Review) 24 Feb '24

24 Feb '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80648?usp=email ) Change subject: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3 ...................................................................... crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3 Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum A util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e90117c..9470fe3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -43,7 +43,7 @@ IASL_VERSION="R06_28_23" # CLANG version number CLANG_VERSION=17.0.6 -CMAKE_VERSION=3.27.7 +CMAKE_VERSION=3.28.3 NASM_VERSION=2.16.01 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum b/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum deleted file mode 100644 index 691bc61..0000000 --- a/util/crossgcc/sum/cmake-3.27.7.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -1b170ceae7fc9659b2cad7e1d8121b370acd5cf2 tarballs/cmake-3.27.7.tar.gz diff --git a/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum new file mode 100644 index 0000000..dc518a9 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum @@ -0,0 +1 @@ +cf332727ac863cc0c86ac4f8cd3b711d05a5e417 tarballs/cmake-3.28.3.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/80648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Gerrit-Change-Number: 80648 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
by Felix Singer (Code Review) 24 Feb '24

24 Feb '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80648?usp=email ) Change subject: crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Gerrit-Change-Number: 80648 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 24 Feb 2024 22:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: Add ASUS h110m-adp
by Máté Kukri (Code Review) 24 Feb '24

24 Feb '24

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80743?usp=email ) Change subject: Add ASUS h110m-adp ...................................................................... Add ASUS h110m-adp Change-Id: If03b11cd6789474939e81c10661253869ef3fc9a --- M src/Kconfig A src/mainboard/asus/h110m-adp/Kconfig A src/mainboard/asus/h110m-adp/Kconfig.name A src/mainboard/asus/h110m-adp/Makefile.mk A src/mainboard/asus/h110m-adp/acpi/dptf.asl A src/mainboard/asus/h110m-adp/acpi/ec.asl A src/mainboard/asus/h110m-adp/acpi/mainboard.asl A src/mainboard/asus/h110m-adp/acpi/superio.asl A src/mainboard/asus/h110m-adp/board_info.txt A src/mainboard/asus/h110m-adp/bootblock.c A src/mainboard/asus/h110m-adp/cmos.default A src/mainboard/asus/h110m-adp/cmos.layout A src/mainboard/asus/h110m-adp/data.vbt A src/mainboard/asus/h110m-adp/devicetree.cb A src/mainboard/asus/h110m-adp/dsdt.asl A src/mainboard/asus/h110m-adp/gma-mainboard.ads A src/mainboard/asus/h110m-adp/hda_verb.c A src/mainboard/asus/h110m-adp/include/gpio.h A src/mainboard/asus/h110m-adp/mainboard.c A src/mainboard/asus/h110m-adp/ramstage.c A src/mainboard/asus/h110m-adp/romstage.c 21 files changed, 803 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80743/1 diff --git a/src/Kconfig b/src/Kconfig index 2bcc3ce..2d7a5fb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -763,7 +763,7 @@ config STACK_SIZE hex - default 0x2000 if ARCH_X86 + default 0x10000 if ARCH_X86 default 0x0 config MAX_CPUS diff --git a/src/mainboard/asus/h110m-adp/Kconfig b/src/mainboard/asus/h110m-adp/Kconfig new file mode 100644 index 0000000..ddb9d35 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/Kconfig @@ -0,0 +1,40 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_H110M_ADP + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_LIBGFXINIT + +config CBFS_SIZE + default 0xd80000 + +config DISABLE_HECI1_AT_PRE_BOOT + default y + +config MAINBOARD_DIR + default "asus/h110m-adp" + +config MAINBOARD_PART_NUMBER + default "H110M-A/DP" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + default 512 #DDR4 + +endif diff --git a/src/mainboard/asus/h110m-adp/Kconfig.name b/src/mainboard/asus/h110m-adp/Kconfig.name new file mode 100644 index 0000000..c852250 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASUS_H110M_ADP + bool "H110M-A/DP" diff --git a/src/mainboard/asus/h110m-adp/Makefile.mk b/src/mainboard/asus/h110m-adp/Makefile.mk new file mode 100644 index 0000000..e8ff53e --- /dev/null +++ b/src/mainboard/asus/h110m-adp/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110m-adp/acpi/dptf.asl b/src/mainboard/asus/h110m-adp/acpi/dptf.asl new file mode 100644 index 0000000..bec32ae --- /dev/null +++ b/src/mainboard/asus/h110m-adp/acpi/dptf.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asus/h110m-adp/acpi/ec.asl b/src/mainboard/asus/h110m-adp/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/h110m-adp/acpi/mainboard.asl b/src/mainboard/asus/h110m-adp/acpi/mainboard.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/h110m-adp/acpi/superio.asl b/src/mainboard/asus/h110m-adp/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asus/h110m-adp/board_info.txt b/src/mainboard/asus/h110m-adp/board_info.txt new file mode 100644 index 0000000..340e2ab --- /dev/null +++ b/src/mainboard/asus/h110m-adp/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/h110m-adp/helpdesk_cpu/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/asus/h110m-adp/bootblock.c b/src/mainboard/asus/h110m-adp/bootblock.c new file mode 100644 index 0000000..17cee5b --- /dev/null +++ b/src/mainboard/asus/h110m-adp/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110m-adp/cmos.default b/src/mainboard/asus/h110m-adp/cmos.default new file mode 100644 index 0000000..84236aa --- /dev/null +++ b/src/mainboard/asus/h110m-adp/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asus/h110m-adp/cmos.layout b/src/mainboard/asus/h110m-adp/cmos.layout new file mode 100644 index 0000000..cff042a --- /dev/null +++ b/src/mainboard/asus/h110m-adp/cmos.layout @@ -0,0 +1,55 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110m-adp/data.vbt b/src/mainboard/asus/h110m-adp/data.vbt new file mode 100644 index 0000000..8267989 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110m-adp/devicetree.cb b/src/mainboard/asus/h110m-adp/devicetree.cb new file mode 100644 index 0000000..2749891 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/devicetree.cb @@ -0,0 +1,200 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "PrimaryDisplay" = "Display_PEG" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # PL2 override 91W + register "power_limits_config" = "{ .tdp_pl2_override = 91, }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on end + + device domain 0 on + # Host bridge + device pci 00.0 on end + + # PCIe x16 + device pci 01.0 on + end + + # Intel iGPU + device pci 02.0 on end + + # XHCI controller + device pci 14.0 on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), + [1] = USB2_PORT_MID(OC0), + [2] = USB2_PORT_MID(OC4), + [3] = USB2_PORT_MID(OC4), + [4] = USB2_PORT_MID(OC2), + [5] = USB2_PORT_MID(OC2), + [6] = USB2_PORT_MID(OC0), + [7] = USB2_PORT_MID(OC0), + [8] = USB2_PORT_MID(OC0), + [9] = USB2_PORT_MID(OC0), + [10] = USB2_PORT_MID(OC1), + [11] = USB2_PORT_MID(OC1), + [12] = USB2_PORT_MID(OC_SKIP), + [13] = USB2_PORT_MID(OC_SKIP), + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), + [1] = USB3_PORT_DEFAULT(OC0), + [2] = USB3_PORT_DEFAULT(OC3), + [3] = USB3_PORT_DEFAULT(OC3), + [4] = USB3_PORT_DEFAULT(OC1), + [5] = USB3_PORT_DEFAULT(OC1), + [6] = USB3_PORT_DEFAULT(OC_SKIP), + [7] = USB3_PORT_DEFAULT(OC_SKIP), + [8] = USB3_PORT_DEFAULT(OC_SKIP), + [9] = USB3_PORT_DEFAULT(OC_SKIP), + }" + end + + # ME inteface + device pci 16.0 on end + + # SATA + device pci 17.0 on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + end + + # PCIe 1x #1 + device pci 1c.0 on + end + + # Realtek LAN + device pci 1c.7 on + end + + # PCIe 1x #2 + device pci 1d.0 on + end + + # LPC + device pci 1f.0 on + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct5539d + device pnp 2e.1 on + irq 0x13 = 0xff + irq 0x14 = 0xff + irq 0x1a = 0x00 + irq 0x1c = 0x73 + + irq 0x24 = 0x00 + irq 0x26 = 0x00 + irq 0x27 = 0x01 + irq 0x28 = 0x10 + irq 0x2a = 0x00 + + irq 0x2c = 0x08 + irq 0x2d = 0x02 + irq 0x2f = 0x00 + end + device pnp 2e.2 on # UART + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 0xc # Mouse + irq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT1 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDT3 + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0x5f + irq 0xe1 = 0x00 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + # HWM reset source=LRESET# + # EN_ONPSOUT=1 + irq 0xe7 = 0x11 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + # Enable FANIN input de-bouncers + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # WDT2 + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.11 off end # GPIO, RI PSOUT Wake-Up Status + device pnp 2e.12 off end # SW Error Control + device pnp 2e.15 off end # Fading LED + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + end + end + end + + # TPM module + chip drivers/pc80/tpm + device pnp 4e.0 on end + end + end + + # HD Audio + device pci 1f.3 on + register "PchHdaVcType" = "Vc1" + end + + # SMBus + device pci 1f.4 on end + end +end diff --git a/src/mainboard/asus/h110m-adp/dsdt.asl b/src/mainboard/asus/h110m-adp/dsdt.asl new file mode 100644 index 0000000..b02708f --- /dev/null +++ b/src/mainboard/asus/h110m-adp/dsdt.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110m-adp/gma-mainboard.ads b/src/mainboard/asus/h110m-adp/gma-mainboard.ads new file mode 100644 index 0000000..bd3e5e9 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110m-adp/hda_verb.c b/src/mainboard/asus/h110m-adp/hda_verb.c new file mode 100644 index 0000000..8601edb --- /dev/null +++ b/src/mainboard/asus/h110m-adp/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x104386c7, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104386c7), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x40330000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4046c629), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x58560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110m-adp/include/gpio.h b/src/mainboard/asus/h110m-adp/include/gpio.h new file mode 100644 index 0000000..0a9acf0 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/include/gpio.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_A14, DN_20K, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_A16, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A19, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A21, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, DN_20K, RSMRST, OFF, ACPI), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B1, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B12, DN_20K, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_B16, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C10, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D1, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D19, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, DN_20K, RSMRST, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, DN_20K, RSMRST, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F1, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F2, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F3, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F11, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F12, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F19, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F20, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F22, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F23, DN_20K, RSMRST, OFF, ACPI), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G18, DN_20K, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G19, DN_20K, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G20, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G22, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, DN_20K, RSMRST, OFF, ACPI), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H7, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H10, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H11, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H13, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H17, DN_20K, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPD6, DN_20K, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPD9, DN_20K, PWROK, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, DN_20K, RSMRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/asus/h110m-adp/mainboard.c b/src/mainboard/asus/h110m-adp/mainboard.c new file mode 100644 index 0000000..f0dbc3f --- /dev/null +++ b/src/mainboard/asus/h110m-adp/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h110m-adp/ramstage.c b/src/mainboard/asus/h110m-adp/ramstage.c new file mode 100644 index 0000000..1a30ecc --- /dev/null +++ b/src/mainboard/asus/h110m-adp/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; +} diff --git a/src/mainboard/asus/h110m-adp/romstage.c b/src/mainboard/asus/h110m-adp/romstage.c new file mode 100644 index 0000000..aec7925 --- /dev/null +++ b/src/mainboard/asus/h110m-adp/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = { 121, 75, 100 }; + + const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If03b11cd6789474939e81c10661253869ef3fc9a Gerrit-Change-Number: 80743 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7
by Felix Held (Code Review) 24 Feb '24

24 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80701?usp=email ) Change subject: soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7 ...................................................................... soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7 Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping". Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/include/soc/southbridge.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h index 9cd835b..b7ac8a8 100644 --- a/src/soc/amd/glinda/include/soc/southbridge.h +++ b/src/soc/amd/glinda/include/soc/southbridge.h @@ -87,7 +87,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_OUTPUT_AVAILABLE 4 +#define GPP_CLK_OUTPUT_AVAILABLE 7 #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) -- To view, visit https://review.coreboot.org/c/coreboot/+/80701?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Gerrit-Change-Number: 80701 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device
by CoolStar (Code Review) 24 Feb '24

24 Feb '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80718?usp=email ) Change subject: soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80718/comment/846cde83_1986093a : PS1, Line 9: Backport 9c348a7b7ea3422a74af9b820275751e9abb4a12 from Alder Lake to > > `Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'comm […] fixed https://review.coreboot.org/c/coreboot/+/80718/comment/43c6a80e_1d3c9a70 : PS1, Line 10: fix a similar issue present on Tiger Lake > Please add a dot/period at the end of sentences. fixed https://review.coreboot.org/c/coreboot/+/80718/comment/f2e97ff9_a4e06183 : PS1, Line 11: > It’d be great if you copied the other commit message to ease review. fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/80718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5409111d4239be86c0b153f01b4fe5fc6af352c Gerrit-Change-Number: 80718 Gerrit-PatchSet: 2 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 24 Feb 2024 19:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/common/acpi/upep: Fix UUID conditional and add notifications ...
by Felix Held (Code Review) 24 Feb '24

24 Feb '24

Attention is currently required from: CoolStar, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77742?usp=email ) Change subject: soc/amd/common/acpi/upep: Fix UUID conditional and add notifications required for Windows Modern Standby notifications ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > It’d be great to get these in? it's still sort-of on my todo list to look into this, but this topic is a bit complicated, since there have been 3 versions of how things are done here. at least we're down to only two versions being used by now though -- To view, visit https://review.coreboot.org/c/coreboot/+/77742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3adf74c613ae2a00a3e8fa6707c40ff2c6b3401 Gerrit-Change-Number: 77742 Gerrit-PatchSet: 4 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 24 Feb 2024 19:26:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASL
by CoolStar (Code Review) 24 Feb '24

24 Feb '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80719?usp=email ) Change subject: soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASL ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80719/comment/56dbc3cc_592dc04e : PS1, Line 9: Backport > By the way, why “backport” and not just “port”? Either way is fine, I just went with backport since ADL is a newer platform than TGL https://review.coreboot.org/c/coreboot/+/80719/comment/56fb4d41_4f2c0ab8 : PS1, Line 14: Verify TCSS XHCI power management : working > How can this be tested? Device Manager no longer Code 43's on default settings (Controller has the option to "Allow the computer to turn off this device to save power" enabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/80719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1 Gerrit-Change-Number: 80719 Gerrit-PatchSet: 3 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 24 Feb 2024 19:26:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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