Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80331?usp=email )
Change subject: mb/google/rex/var/karis: Update fw_config KB_TYPE field
......................................................................
mb/google/rex/var/karis: Update fw_config KB_TYPE field
Update element "KB_TYPE_CA" for align fw_config.
Only EC will reference KB_TYPE field in fw_config. This
CL is just for align fw_config.
BUG=none
TEST=emerge coreboot pass
Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde
Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/rex/variants/karis/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/80331/1
diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb
index 371109a..fcff2c9 100644
--- a/src/mainboard/google/rex/variants/karis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/karis/overridetree.cb
@@ -24,6 +24,7 @@
end
field KB_TYPE 12
option KB_TYPE_DEFAULT 0
+ option KB_TYPE_CA 1
end
field WIFI_TYPE 13
option WIFI_CNVI 0
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Change subject: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80328/comment/8700d8f4_9ee78478 :
PS3, Line 8:
> I’d be nice, if you elaborated more, what the problem is.
Same comment as Patrick’s, so mark this one as *Resolved*.
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Change subject: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80328/comment/caa541c7_edefea10 :
PS3, Line 8:
I’d be nice, if you elaborated more, what the problem is.
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80328/comment/e5a136ea_8a698c30 :
PS3, Line 42: FSP_DOES_NOT_NEED_TEMP_RAM
Personally I’d prefer non-negative names, that means without `NOT`.
https://review.coreboot.org/c/coreboot/+/80328/comment/21c3a29a_7245d35c :
PS3, Line 46: FSP allocates temporary ram in its reserved memory ranges
: instead of requesting coreboot to do the allocation.
The option says `NOT_NEED`? Isn’t that a contradiction?
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
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Patch Set 10: Code-Review+1
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80277/comment/edfd363d_3e584612 :
PS8, Line 28: Fortunately, EDK2 header allows to override the EFIAPI
: definition. The __ms_abi__ attribute works for both i386 and x86_64.
:
Not true on clang and it also does not match what the code is doing.
File src/include/efi/efi_datatype.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/b8e3ea65_93de0f64 :
PS8, Line 65: /* Status codes common to all execution phases */
duplicated comment.
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Hello Andrey Petrov, Angel Pons, Damien Zammit, Felix Held, Huang Jin, Lee Leahy, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review-1 by Arthur Heymans
Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook
......................................................................
lib/romstage_handoff.c: Initialize using a cbmem hook
This reduces platform boilerplate code.
This also drops outdated comments and unused parameters.
Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/include/romstage_handoff.h
M src/lib/romstage_handoff.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/haswell/romstage.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/x4x/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/romstage.c
15 files changed, 13 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/7
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Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
File src/lib/romstage_handoff.c:
https://review.coreboot.org/c/coreboot/+/52933/comment/e6e79423_4dfd8636 :
PS3, Line 56: ROMSTAGE_CBMEM_INIT_HOOK(romstage_handoff_init);
> > Since this file is compiled unconditionally, adding an INIT_HOOK() expands this to a lot of platforms which never used it. Please add a Kconfig to limit compilation of the file to the right set of boards if you want to do this (I'm not quite sure what exactly this is or what the right set of boards for it would be, but I know the Arm boards I work on don't use this, for example).
>
> Done. HAVE_ACPI_RESUME is the proper flag.
Hmm there are other flags in there.
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Hello Andrey Petrov, Angel Pons, Damien Zammit, Felix Held, Huang Jin, Lee Leahy, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, build bot (Jenkins),
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Change subject: lib/romstage_handoff.c: Initialize using a cbmem hook
......................................................................
lib/romstage_handoff.c: Initialize using a cbmem hook
This reduces platform boilerplate code.
Change-Id: I93abf33a6eb055eeaba1fed5042387822de1aa20
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/include/romstage_handoff.h
M src/lib/romstage_handoff.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/haswell/romstage.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/x4x/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/romstage.c
15 files changed, 11 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52933/6
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