coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: brox: Handle GPI_INT pin value lower to GPI_WAKE
by Ashish Kumar Mishra (Code Review) 02 Feb '24

02 Feb '24

Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80334?usp=email ) Change subject: brox: Handle GPI_INT pin value lower to GPI_WAKE ...................................................................... brox: Handle GPI_INT pin value lower to GPI_WAKE In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/80334/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 5432bd1..3f39f18 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -140,7 +140,7 @@ PAD_NC(GPP_C7, NONE), /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ - PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL), /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */ diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 63d59da..1f56832 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -276,7 +276,8 @@ * in the GPIO pad configuration so that a hardware active low * signal looks that way to the APIC (double inversion). */ - if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) + if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED) && + !(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) return; irq = pcr_read32(port, PAD_CFG1_OFFSET(pad_cfg_offset)); @@ -287,7 +288,8 @@ return; } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG) && + !(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED)) itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT)); @@ -349,6 +351,7 @@ } config_offset = pad_config_offset(comm, cfg->pad); + pin = relative_pad_in_comm(comm, cfg->pad); group = gpio_group_index(comm, pin); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 654d6f2..2a7801f 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -44,6 +44,7 @@ #define PAD_CFG0_ROUTE_SMI (1 << 18) #define PAD_CFG0_ROUTE_SCI (1 << 19) #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_ROUTE_SWAPPED (1 << 27) #define PAD_CFG0_RXTENCFG_MASK (3 << 21) #define PAD_CFG0_RXINV_MASK (1 << 23) #define PAD_CFG0_RX_POL_INVERT (1 << 23) @@ -336,12 +337,24 @@ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#define PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | PAD_IRQ_ROUTE(SWAPPED), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) + #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \ _PAD_CFG_STRUCT_LOCK(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) +#define PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, rst, trig, own, lock_action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | PAD_IRQ_ROUTE(SWAPPED), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) + #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ @@ -370,10 +383,16 @@ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) +#define PAD_CFG_GPI_INT_SWAPPED(pad, pull, rst, trig) \ + PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, DRIVER) + /* GPIO Interrupt with lock */ #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \ PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action) +#define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action) \ + PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action) + /* * No Connect configuration for unconnected or unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary -- To view, visit https://review.coreboot.org/c/coreboot/+/80334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Gerrit-Change-Number: 80334 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: cpu/x86/smm/pci_resource_store: Allow devices with no resources
by Martin L Roth (Code Review) 02 Feb '24

02 Feb '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80246?usp=email ) Change subject: cpu/x86/smm/pci_resource_store: Allow devices with no resources ...................................................................... cpu/x86/smm/pci_resource_store: Allow devices with no resources When a device with no resource is passed it will keep overwriting the current slot. Remove the conditional and allow a PCI device to not have any resources. This is particular useful for the next commits that makes use of the PCI resource store to pass UBOX devices to SMM that allow to lock-down SMM from within an SMI handler. Those devices do not have any resources and cannot be hardcoded in SMM as their PCI segment group and bus number varies depending on socket count, CPU discovery and configuration. Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80246 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/cpu/x86/smm/pci_resource_store.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/smm/pci_resource_store.c b/src/cpu/x86/smm/pci_resource_store.c index f1d3e28..b1e61a9 100644 --- a/src/cpu/x86/smm/pci_resource_store.c +++ b/src/cpu/x86/smm/pci_resource_store.c @@ -37,10 +37,6 @@ slots[i_slot].vendor_id = devices[i_dev]->vendor; slots[i_slot].device_id = devices[i_dev]->device; - /* Use the resource list to get our BARs. */ - if (!devices[i_dev]->resource_list) - continue; - size_t i_res = 0; for (const struct resource *res = devices[i_dev]->resource_list; res != NULL; res = res->next) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5 Gerrit-Change-Number: 80246 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: cpu/x86/smm/pci_resource_store: Allow devices with no resources
by Martin L Roth (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Jérémy Compostella, Patrick Rudolph. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80246?usp=email ) Change subject: cpu/x86/smm/pci_resource_store: Allow devices with no resources ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5 Gerrit-Change-Number: 80246 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Feb 2024 14:46:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [RFC] util/showdevicetree: drop unmaintained tool
by Martin L Roth (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79934?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: [RFC] util/showdevicetree: drop unmaintained tool ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79934/comment/e4d0b454_3ee32049 : PS3, Line 7: [RFC] Patch seems good to me. Drop the RFC before it's merged? -- To view, visit https://review.coreboot.org/c/coreboot/+/79934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e Gerrit-Change-Number: 79934 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Feb 2024 14:43:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/gma: Add missing parentheses to brightness ACPI
by Martin L Roth (Code Review) 02 Feb '24

02 Feb '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80260?usp=email ) Change subject: drivers/intel/gma: Add missing parentheses to brightness ACPI ...................................................................... drivers/intel/gma: Add missing parentheses to brightness ACPI Commit d25277666829 ("tree: Replace And(a,b) with ASL 2.0 syntax") replaced two instances of `And(var, mask) == 0` with `var & mask == 0`. This expression needs parentheses - `(var & mask) == 0`. Without parentheses, it is always false, since the masks are nonzero (`var & (mask == 0)`; `var & 0`; `0`). This caused brightness changes on Intel GMA to take longer than normal since the status was never checked. The brightness would change immediately, but another brightness change could not occur until the first change timed out. This was most noticeable in KDE, which waits for the brightness change to complete before accepting another brightness up/down keypress. Tapping brightness up/down repeatedly would take much longer to reach max/min brightness due to many presses being ignored. It is noticeable in GNOME as well but less obvious. Tapping brightness up/down repeatedly would handle all keypresses, but the display's actual brightness would lag behind and skip some intermediate steps. I tested both Librem 13v2 and Librem 14, as far as I know this would apply to all systems configuring brightness with Intel GMA. Test: Verify brightness keys respond quickly again on Librem 13v2 / 14. Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80260 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index d6e417c..3a097e3 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -46,7 +46,7 @@ { Return (Ones) } - If (MBOX & 4 == 0) + If ((MBOX & 4) == 0) { Return (Ones) } @@ -74,7 +74,7 @@ While (Local0 > 0) { Sleep (1) - If (ASLC & 2 == 0) { + If ((ASLC & 2) == 0) { /* Request has been processed, check status: */ Local1 = (ASLC >> 12) & 3 If (Local1 == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Gerrit-Change-Number: 80260 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: cpu/x86: Add 1GiB pages for memory access up to 512GiB
by Ashish Kumar Mishra (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80088?usp=email ) Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ...................................................................... Patch Set 7: (3 comments) Patchset: PS7: Rewrote the PDE table to match existing 2MB page impl. File src/cpu/x86/64bit/pt1G.S: https://review.coreboot.org/c/coreboot/+/80088/comment/1204f8b9_8958e750 : PS6, Line 19: PM > align to 32 Done https://review.coreboot.org/c/coreboot/+/80088/comment/933719a9_1ad86479 : PS6, Line 23: 16 > needs to align to 4096 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Gerrit-Change-Number: 80088 Gerrit-PatchSet: 7 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 02 Feb 2024 14:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Add 1GiB pages for memory access up to 512GiB
by Ashish Kumar Mishra (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim. Hello Arthur Heymans, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80088?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review-1 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ...................................................................... cpu/x86: Add 1GiB pages for memory access up to 512GiB Current pagetable implementation allows memory access up to 4GiB using 2MiB pages. If user wants to access more than 4GiB with a 2MiB page it will require more pagetable entries. By using a 1GiB page table, users can access more than 4GiB of memory while reducing the number of pagetable entries. This patch enables memory access up to 512GiB through 1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig. TEST: Verified in 64bit mode boot and access above 4GiB Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Gerrit-Change-Number: 80088 Gerrit-PatchSet: 7 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer
by 9elements QA (Code Review) 02 Feb '24

02 Feb '24

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80269?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/198744 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/198742 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/198741 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/198740 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/198739 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/198738 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/198737 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/198736 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/198735 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/198734 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/198733 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/198732 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/80269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Gerrit-Change-Number: 80269 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 14:15:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Update fw_config KB_TYPE field
by Subrata Banik (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80331?usp=email ) Change subject: mb/google/rex/var/karis: Update fw_config KB_TYPE field ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde Gerrit-Change-Number: 80331 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 14:07:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/azalia: Rework the verb table
by Nicholas Sudsgaard (Code Review) 02 Feb '24

02 Feb '24

Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80333?usp=email ) Change subject: device/azalia: Rework the verb table ...................................................................... Patch Set 2: (2 comments) File src/device/azalia_device.c: https://review.coreboot.org/c/coreboot/+/80333/comment/57925631_32b85e57 : PS2, Line 106: * Find a specific entry within a verb table Not sure if I should keep this comment. File src/include/device/azalia_device.h: https://review.coreboot.org/c/coreboot/+/80333/comment/4dd15335_db094318 : PS2, Line 21: #define HDA_MAX_CORBSIZE 256 Not sure when to use the HDA_ prefix and the AZALIA_ prefix. -- To view, visit https://review.coreboot.org/c/coreboot/+/80333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8b672e4fd800b34e5ba39fad174fcf1154b0a54 Gerrit-Change-Number: 80333 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2024 13:41:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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