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Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I guess with the public EGS FSP, coreboot + UEFI payload should be able to boot OS.
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I'd like you to reexamine a change. Please visit
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Change subject: device_tree: Add function to get top of memory from a FDT blob
......................................................................
device_tree: Add function to get top of memory from a FDT blob
coreboot needs to figure out top of memory to place CBMEM data. On some
non-x86 QEMU virtual machines, this is achieved by probing the RAM space
to find where the VM starts discarding data since it's not backed by
actual RAM. This behaviour seems to have changed on the QEMU side since
then, VMs using the "virt" model have started raising exceptions/errors
instead of silently discarding data (likely [1] for example) which has
broken coreboot on these emulation boards.
The qemu-aarch64 mainboard is intended for the "virt" model and had this
issue, which was fixed by using exception handlers in the RAM detection
process [2].
The qemu-riscv mainboard is also for "virt" and still has this issue.
There is a potential fix based on the exception handler approach [3],
but it fails to build for 32-bit RISC-V. There's also a WIP attempt on
parsing the in-memory device-tree that QEMU provides us [4], but it
relies on unflattening which wouldn't work on romstage.
The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM
which doesn't appear to suffer from this issue. Still, the issue can be
observed on the ARMv7 "virt" model via a port based on qemu-aarch64.
QEMU docs for ARM and RISC-V "virt" models [5][6] recommend reading the
device tree blob it provides for device information (incl. RAM size).
Implement a function that parses the device tree blob to find the top of
memory in order to use it in mainboard code as an alternative to probing
RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't
available, so take care to do parsing without unflattening the blob and
make the code available in romstage as well.
This assumes a single memory node with a single reg range which seems
to be enough for what QEMU provides for now, support for more complex
device-trees (as supported by specification) is left as future work.
[1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.…
[2] https://review.coreboot.org/c/coreboot/+/34774
[3] https://review.coreboot.org/c/coreboot/+/36486
[4] https://review.coreboot.org/c/coreboot/+/78981
[5] https://qemu-project.gitlab.io/qemu/system/arm/virt.html
[6] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html
Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
---
M src/include/device_tree.h
M src/lib/Makefile.mk
M src/lib/device_tree.c
3 files changed, 102 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80322/3
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Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
device/pciexp_device.c: Fix setting Max Payload Size
Current implementation assumes that the endpoint device is connected
directly to the PCIe Root Port, which does not always have to be true.
In a case where there is a PCIe switch between the endpoint and the
root port, the Max Payload Size capability may differ across the
devices in the chain and coreboot will not set a correct Max Payload
Size. This results in a PCIe device malfunction in pre-OS environment,
e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE
fails to obtain the DHCP configuration.
Fix this by traversing the topology and programming the highest common
Max Payload Size in the given PCIe device chain during enumeration.
Once finished, the root port has the highest common Max Payload Size
supported by all the devices in the chain. So at the end of root port
bus scan, propagate the root port's Max Payload Size to all downstream
devices to keep Max Payload Size in sync within the whole chain.
TEST=Perform successful dhcp command in iPXE on the NIC connected to
the PCIe root port via ASMedia ASM1806 PCIe switch and again on the
NIC connected directly to the PCIe root port.
Change-Id: I24386dc208363b7d94fea46dec25c231a3968225
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/device/pciexp_device.c
1 file changed, 129 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/17
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
Patch Set 16:
(5 comments)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/c056e7a8_dceb4526 :
PS15, Line 638: pciexp_dev_set_max_payload_size(child, max_payload);
> Shouldn't be necessary as that's what we'll do with pciexp_sync_max_payload_size().
Indeed, we only care about the MPS propagation upwards. Removed.
https://review.coreboot.org/c/coreboot/+/77338/comment/53dc2160_b2d34bd3 :
PS15, Line 641: if (max_payload != child_max_payload)
: printk(BIOS_INFO, "%s: Max_Payload_Size adjusted to %d\n", dev_path(child),
: (1 << (max_payload + 7)));
> This too could be dropped then.
Removed.
https://review.coreboot.org/c/coreboot/+/77338/comment/b5d8daf6_0fa66bbd :
PS15, Line 691: };
> I still don't see why we would need a loop. pciexp_tune_dev() will be called […]
The whole function is not needed at all actually. AS you have pointed out, we already set the MPS recursively upwards.
https://review.coreboot.org/c/coreboot/+/77338/comment/448c3553_587c5a2c :
PS15, Line 728: pciexp_dev_set_max_payload_size(dev, pciexp_dev_get_max_payload_size_cap(dev));
> If I'm not mistaken, `dev` could be a bridge that already has its […]
Yes, limited it to express endpoints and legacy endpoints.
https://review.coreboot.org/c/coreboot/+/77338/comment/4fc6d068_b486ca15 :
PS15, Line 740: pciexp_dev_set_max_payload_size(bus->dev, max_payload);
> This step seems redundant. Because for the first call of […]
Right, not sure what I was thinking... Removed.
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I'd like you to reexamine a change. Please visit
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
device/pciexp_device.c: Fix setting Max Payload Size
Current implementation assumes that the endpoint device is connected
directly to the PCIe Root Port, which does not always have to be true.
In a case where there is a PCIe switch between the endpoint and the
root port, the Max Payload Size capability may differ across the
devices in the chain and coreboot will not set a correct Max Payload
Size. This results in a PCIe device malfunction in pre-OS environment,
e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE
fails to obtain the DHCP configuration.
Fix this by traversing the topology and programming the highest common
Max Payload Size in the given PCIe device chain during enumeration.
Once finished, the root port has the highest common Max Payload Size
supported by all the devices in the chain. So at the end of root port
bus scan, propagate the root port's Max Payload Size to all downstream
devices to keep Max Payload Size in sync within the whole chain.
TEST=Perform successful dhcp command in iPXE on the NIC connected to
the PCIe root port via ASMedia ASM1806 PCIe switch and again on the
NIC connected directly to the PCIe root port.
Change-Id: I24386dc208363b7d94fea46dec25c231a3968225
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/device/pciexp_device.c
1 file changed, 129 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/16
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Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68843?usp=email )
Change subject: mb/emulation/riscv: Limit DRAM size
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> I agree we may be better of just adding libfdt so we don't always need to unflatten it. […]
oh wait. I always confuse the naming scheme. You can also use FDT in coreboot without any heap usage. The `fdt_` prefixed functions should not do any unflatten but just directly read the blob. The `dt_` prefixed functions are only working on our internal `struct device_tree` representation and therefore require an unflatten of the blob.
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Change subject: device_tree: Add function to get top of memory from a FDT blob
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Fixed `'coreboot' should be lowercase in commit message`, but I don't know how to trigger Jenkins' check again.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: device_tree: Add function to get top of memory from a FDT blob
......................................................................
device_tree: Add function to get top of memory from a FDT blob
coreboot needs to figure out top of memory to place CBMEM data. On some
non-x86 QEMU virtual machines, this is achieved by probing the RAM space
to find where the VM starts discarding data since it's not backed by
actual RAM. This behaviour seems to have changed on the QEMU side since
then, VMs using the "virt" model have started raising exceptions/errors
instead of silently discarding data (likely [1] for example) which has
broken coreboot on these emulation boards.
The qemu-aarch64 mainboard is intended for the "virt" model and had this
issue, which was fixed by using exception handlers in the RAM detection
process [2].
The qemu-riscv mainboard is also for "virt" and still has this issue.
There is a potential fix based on the exception handler approach [3],
but it fails to build for 32-bit RISC-V. There's also a WIP attempt on
parsing the in-memory device-tree that QEMU provides us [4], but it
relies on unflattening which wouldn't work on romstage.
The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM
which doesn't appear to suffer from this issue. Still, the issue can be
observed on the ARMv7 "virt" model via a port based on qemu-aarch64.
QEMU docs for ARM and RISC-V "virt" models [5][6] recommend reading the
device tree blob it provides for device information (incl. RAM size).
Implement a function that parses the device tree blob to find the top of
memory in order to use it in mainboard code as an alternative to probing
RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't
available, so take care to do parsing without unflattening the blob and
make the code available in romstage as well.
This assumes a single memory node with a single reg range which seems
to be enough for what QEMU provides for now, support for more complex
device-trees (as supported by specification) is left as future work.
[1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.…
[2] https://review.coreboot.org/c/coreboot/+/34774
[3] https://review.coreboot.org/c/coreboot/+/36486
[4] https://review.coreboot.org/c/coreboot/+/78981
[5] https://qemu-project.gitlab.io/qemu/system/arm/virt.html
[6] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html
Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
---
M src/include/device_tree.h
M src/lib/Makefile.mk
M src/lib/device_tree.c
3 files changed, 102 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80322/2
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Change subject: mainboard/qemu-riscv: Select framebuffer related kconfigs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/emulation/qemu-riscv/Kconfig:
https://review.coreboot.org/c/coreboot/+/80380/comment/c1676fa3_3a0bf1e0 :
PS1, Line 32: select HAVE_LINEAR_FRAMEBUFFER
Depends on CB:80376
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