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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 2:
(4 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/80343/comment/6f124800_3782d87c :
PS1, Line 7: WIP:
> You can use the Gerrit tag for the change-set, so you do not have to update the commit message.
Done
https://review.coreboot.org/c/coreboot/+/80343/comment/6b3d3a2e_1c61c972 :
PS1, Line 7: Add ThinkCentre M710s
> Maybe mention the SoC too: […]
Done
https://review.coreboot.org/c/coreboot/+/80343/comment/750247da_286529da :
PS1, Line 10: - Can boot Ubuntu using payloads: SeaBIOS, TianoCore EDK 2
> I’d be great if you mentioned the versions (also Linux kernel).
Done
Patchset:
PS1:
> Great work by the way. Great to have you in the coreboot community.
Thanks 😊
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Change subject: mb/emulation/riscv: Limit DRAM size
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> oh wait. I always confuse the naming scheme. […]
I've been working on getting RAM size from FDT, uploaded now as CB:80322 (along with more ARM64/RISC-V QEMU patches). Please have a look.
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Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
......................................................................
Patch Set 5: Code-Review+2
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Change subject: cpu/qemu-x86/cache_as_ram: Move guard
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mainboard/qemu-riscv: Get top of memory from device-tree blob
......................................................................
Patch Set 2:
(1 comment)
File src/soc/ucb/riscv/cbmem.c:
https://review.coreboot.org/c/coreboot/+/80363/comment/ebba1a94_11677fc4 :
PS2, Line 13: top = fdt_get_memory_top((void *)HLS()->fdt);
Breaks mb/spike-riscv build. I don't have any experience with it so don't know what best to do, thinking of one of:
- Select FLATTENED_DEVICE_TREE also for spike-riscv (would it work?)
- Use `if (CONFIG(FLATTENED_DEVICE_TREE))`
- Add custom `cbmem.c` to mb/spike-riscv without this
- Add custom `cbmem.c` to mb/qemu-riscv for this
(It also appears to hardcode a 1GiB RAM size in its `mainboard.c`)
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Change subject: arch/riscv: Add OPENSBI_FW_DYNAMIC_BOOT_HART option
......................................................................
arch/riscv: Add OPENSBI_FW_DYNAMIC_BOOT_HART option
This adds another option to tell OpenSBI which hart to use for booting.
Test: Start hifive-unmatched board and see that Hart 1 (instead of 0) is
used for running OpenSBI.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Id58bd6ae3b55a5ef3f1a5c97dfa07c79aa4c78d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79948
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---
M src/arch/riscv/Kconfig
M src/arch/riscv/opensbi.c
2 files changed, 12 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Philipp Hug: Looks good to me, but someone else must approve
Felix Held: Looks good to me, but someone else must approve
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2578b12..e466804 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -66,6 +66,16 @@
help
The linking address used to build opensbi.
+config OPENSBI_FW_DYNAMIC_BOOT_HART
+ int
+ default RISCV_WORKING_HARTID
+ help
+ This specifies the hart that OpenSBI will use to boot the payload. If set to
+ value -1, OpenSBI will use a 'lottery' scheme to figure it out itself.
+ This hart must be able to execute in the Supervisor priviledged mode, since
+ that is the mode usually used for the payload. If the hart does not support
+ Supervisor mode OpenSBI will again look for a hart that does support it.
+
config ARCH_RISCV_U
# U (user) mode is for programs.
bool
diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
index 48f0f2a..bf26b22 100644
--- a/src/arch/riscv/opensbi.c
+++ b/src/arch/riscv/opensbi.c
@@ -20,6 +20,8 @@
.version = FW_DYNAMIC_INFO_VERSION_MAX,
.next_mode = payload_mode,
.next_addr = (uintptr_t)payload,
+ .options = 0,
+ .boot_hart = CONFIG_OPENSBI_FW_DYNAMIC_BOOT_HART,
};
csr_write(mepc, opensbi);
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Change subject: mb/amd/birman: Add Birmanplus board support for PHX1 SOC
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
did you verify that the soc's gpio configuration in gpio.c and the ec's gpio configuration in ec.c are also valid for birmanplus?
File src/mainboard/amd/birman/Kconfig:
https://review.coreboot.org/c/coreboot/+/80353/comment/7bdad66c_8568cb0a :
PS2, Line 78: default "3rdparty/blobs/mainboard/amd/birman/EC_birman.bin"
do birman and birmanplus share the same ec firmware?
File src/mainboard/amd/birman/variants/birmanplus/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/80353/comment/2a01a5bf_7e91d9e4 :
PS2, Line 17:
in a few lines the '\' in these defines aren't aligned; would be good to make sure that those are all aligned
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Change subject: device_tree: Add function to get top of memory from a FDT blob
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Fixed `'coreboot' should be lowercase in commit message`, but I don't know how to trigger Jenkins' c […]
Done by pushing a new version.
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