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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmn/graphics: Use DSM size for calculating GTT offset
......................................................................
soc/intel/cmn/graphics: Use DSM size for calculating GTT offset
This patch overrides the assumption being made by the GFX PEIM blob
between version 1029 and 103x to fix some issue where GTT offset
has calculated based on the eDP panel resoultion rather relying on
the pre-allocated memory limit for IGD.
Now this is causing major blocker for CrOS as GFX PEIM latest version
is no more working with existing OS (causing reboot or blank display).
To fix this issue, coreboot tries to perform an override to restore
PANEL_SURF register to the original value which has calculated based
on pre-allocated memory limit (B0/D0/F0:R 0x50 aka GGC) size.
BUG=b:314887266
TEST=Able to boot to OS where display is functional with latest FSP
(w/ GFX PEIM 1035).
Change-Id: Ied5af0faad73d0c88cab70dee6fe731f1a14653b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/drivers/intel/gma/i915.h
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80405/2
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Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80300/comment/c577a1fe_9486a3ca :
PS4, Line 10: was causing some leakage
Was it measured?
https://review.coreboot.org/c/coreboot/+/80300/comment/61e21fa5_3501d704 :
PS4, Line 10: Configuring it to 0 initially in
: romstage should fix this.
s/should fix/fixes/
?
https://review.coreboot.org/c/coreboot/+/80300/comment/b8e57473_370eeaa7 :
PS4, Line 11: Also, make sure that EN_PP3300_TCHSCR is
: initialized in romstage as well.
Why?
https://review.coreboot.org/c/coreboot/+/80300/comment/ad12b643_e924884a :
PS4, Line 13:
What does the schematic say?
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Change subject: mb/google/brya/var/xol: Update DTT policy
......................................................................
Patch Set 2: Code-Review+2
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Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80410?usp=email
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Verified+1 by build bot (Jenkins)
Change subject: mb/google/brya/var/xol: Update DTT policy
......................................................................
mb/google/brya/var/xol: Update DTT policy
Update initial DTT policy for Xol.
- Critical CPU temparature: 99
- TCC offset: 94
BUG=b:323989520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xol/overridetree.cb
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80410/2
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Change subject: soc/intel/xeon_sp/numa: Store pointer to device
......................................................................
Patch Set 4: Code-Review+2
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Change subject: acpi/acpi: Pass struct device to acpi_create_srat_gia_pci
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/brya/var/xol: Update memory configuration
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ storm
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
Patch Set 14: Code-Review+2
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Hello Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80332?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: device/azalia: Separate codec checking and initialization
......................................................................
device/azalia: Separate codec checking and initialization
This also changes how debug messages will be printed. I focused on
reducing clutter on the screen and made the style of the messages
consistent.
Before:
azalia_audio: Initializing codec #5
codec not ready.
azalia_audio: Initializing codec #4
codec not valid.
azalia_audio: Initializing codec #3
azalia_audio: viddid: ffffffff
azalia_audio: verb_size: 4
azalia_audio: verb loaded.
After:
azalia_audio: codec #5 not ready
azalia_audio: codec #4 not valid
azalia_audio: initializing codec #3...
azalia_audio: - vendor/device id: 0xffffffff
azalia_audio: - verb size: 4
azalia_audio: - verb loaded
Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
2 files changed, 42 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/80332/9
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