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Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_read_public()`
......................................................................
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Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > Basically, I think when you're trying to call write32() with an integer address then in 99% of the […]
Are you arguing that we can't do byte-wise arithmetic with `void *`, or more generally that `void *` shouldn't point to something that's not allocated by the C runtime because of language minutiae in the standard? Either way, I don't think it's a good reason not to use it (and I believe we had the `void *` arithmetic argument before... in fact, we've now put in the coding style that it's fine: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Docu…). The C standard was written 50 years ago and mainly targeted at userspace development, not systems. For firmware development we have to do some things that "violate" it anyway, and we are using other GCC-extensions (which clang also supports) anyway, so I don't think there's a point in clinging too strictly to the letter of the standard for this.
Adding a new type specifically to represent MMIO space means yet another coreboot-specific style detail for new contributors to learn, and I'm not convinced it really adds value to justify it. I think people are used to using `void *` to represent arbitrary addresses (and we also have many instances of MMIO space represented by non-void types, like all the struct overlays that are common on our Arm platforms (e.g. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/src/…). And we have `void *` arithmetic in other cases as well anyway, that's not specific to just MMIO.
(I think the main concern about lack of type safety is that people confuse the order of the address and value arguments, especially since we used to have `writel(val, addr)` functions in the past that had it exactly the other way around, and some other firmware projects still do. Using `void *` at least solves that problem. I think accidentally using some other random pointer is not a common mistake.)
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Change subject: mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
https://review.coreboot.org/c/coreboot/+/80334/comment/221d585c_82a621f6 :
PS3, Line 188: PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
> yes. Any pin that has IOAPIC flag set(in this case it is), will become […]
Ashish, are you saying that if we config GPP_D0 with PAD_CFG_APIC_LOCK it would prevent the IRQ 44 conflict that we were seeing before?
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS3:
> This needs to be rebased on top of your other patch in CB:80344 (superio/ifd: Add IT8629E) so that C […]
I didn't know you could do that (I'm not the best at git). Thanks for the explanation. 😊
File src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/80343/comment/4f467d33_437d5db4 :
PS3, Line 1: GPL-2.0-only
> Should be CC-PDDC, refer to commit cf4722d317 (src/mb: Update unlicensable files with the CC-PDDC SP […]
Makes sense, thanks.
File src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/80343/comment/becdd1c7_77a10b5c :
PS3, Line 1: GPL-2.0-onl
> CC-PDDC
Done
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Hello Alexander Couzens, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80343?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader (Technically just a USB)
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (Headphone jack and via display)
- COM1
- TPM
Not Working:
- Audio (Internal speaker works when headphones are connected to the
rear port??)
- SATA ACPI error
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/early_init.c
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 613 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/4
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80184?usp=email )
Change subject: arch/arm64/armv8: Add exception output without printk
......................................................................
arch/arm64/armv8: Add exception output without printk
In case printk does not work the current exception handler will print a
simple "!" to notify the developer that coreboot is actually there but
something went wrong.
The "!" can be quite confusing when it actually happens that printk does
not work. Since "!" doesn't really say much (if you don't know the
exception arm64 code) the developer (like me) can easily assume that
something went wrong while configuring clocks or baud rate of UART,
since the output seemingly does not seem to make sense.
This adds a little bit more output to assure the developer that what was
printed was actually intended to be printed. Therefore it prints
"EXCEPT" which assures the developer that this was intended output.
It also adds a comment above so that developer can more easily grep
for this message.
It has intentionally not been written as:
```
const char *msg = "\r\n!EXCPT!";
while (*msg)
__uart_tx_byte(*msg++);
```
because in this case the compiler will generate code that will place
`msg` somewhere in bootblock and the code will try to access this using
a memory address. In rare cases (if you link bootblock at the wrong
address) this memory address can be wrong and coreboot will not print
the message. Using individual calls to `__uart_tx_byte` ensures that the
compiler will generate code which directly puts the character bytes into
the argument register without referencing a variable in bootblock.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I2f858730469fff3cae120fd7c32fec53b3d309ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80184
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/arch/arm64/armv8/exception.c
1 file changed, 12 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
index 15d7e38..8583fd5 100644
--- a/src/arch/arm64/armv8/exception.c
+++ b/src/arch/arm64/armv8/exception.c
@@ -101,10 +101,21 @@
static void print_exception_info(struct exc_state *state, uint64_t idx)
{
- /* Poor man's sign of life in case printk() is shot. */
+ /*
+ * Sign of life in case printk() is shot. Prints !EXCEPT! to UART
+ * Not using a loop but instead calling __uart_tx_byte separately is intentionally here
+ * because in rare cases it will not print if it needs to access memory addresses
+ */
__uart_tx_byte('\r');
__uart_tx_byte('\n');
__uart_tx_byte('!');
+ __uart_tx_byte('E');
+ __uart_tx_byte('X');
+ __uart_tx_byte('C');
+ __uart_tx_byte('E');
+ __uart_tx_byte('P');
+ __uart_tx_byte('T');
+ __uart_tx_byte('!');
printk(BIOS_DEBUG, "\nexception %s\n",
idx < NUM_EXC_VIDS ? exception_names[idx] : "_unknown");
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Change subject: 3rdparty/intel-sec-tools: Update submodule pointer and cbnt Makefile
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Just FYI - the current HEAD of converged security suite now depends on an existing tag of Fiano:
https://github.com/9elements/converged-security-suite/commit/d400786fb2772a…
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Change subject: drivers/qemu: Split Cirrus display support from Bochs display support
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/drivers/emulation/qemu/Kconfig:
https://review.coreboot.org/c/coreboot/+/80375/comment/65e9ecd9_c6608c31 :
PS1, Line 26: DRIVERS_EMULATION_QEMU_CIRRUS
> Should Cirrus and Bochs be mutually exclusive?
One could build one image for both and use it with different QEMU settings,
i.e. switching graphics cards is most easy with QEMU :D so, why not allow that?
The right driver would be picked at runtime by PCI ID.
In any case, I don't think we have to duplicate the resolution Kconfigs. Can we
makes those generic DRIVERS_EMULATION_QEMU_X/YRES?
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