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Change subject: drivers/qemu/bochs: Allow building for non-x86 architectures
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/emulation/qemu/bochs.c:
https://review.coreboot.org/c/coreboot/+/80376/comment/9f3f932d_b581acc0 :
PS1, Line 118: VGA
When using the legacy BOCHS VGA, which identifies as PCI_CLASS_DISPLAY_VGA, it must use the legacy VGA resources.
If you don't want legacy VGA resources, don't use BOCHS VGA, use bochs-display.
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Change subject: include/device/device: fix soft_reserved_ram_resource macro
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
So we really merged the soft-reserved stuff...
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/80335/comment/289eca22_30076ff0 :
PS4, Line 366: sp->cr3 = read_cr3();
i wonder if this is really needed to only be run depending on ENV_X86_64. at least to me it seems that it wouldn't hurt to also do that in the ENV_X86_32 case and it would be a bit more consistent
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80305?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/nissa/var/yaviks: Enable USE_MTCL and DRIVERS_MTK_WIFI
......................................................................
mb/google/nissa/var/yaviks: Enable USE_MTCL and DRIVERS_MTK_WIFI
This patch selects the DRIVERS_MTK_WIFI and USE_MTCL configs for google/yaviks as
the first platform that provides a country list to the Linux kernel via an
ACPI function (MTCL) in SSDT for MediaTek WiFi chipsets that are capable of
operating on the 6GHz band.
BUG=b:295544553
TEST=Build on similar model (PUJJO) that I have access to and verify the
flag and feature work as intended.
TEST=Add wifi_mtcls.bin blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Change-Id: Iec54fc582d68b443665fceda47187c28f1a9216c
Signed-off-by: David Ruth <druth(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80305
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
Nico Huber: Looks good to me, but someone else must approve
Kapil Porwal: Looks good to me, approved
Subrata Banik: Looks good to me, approved
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 297e0b4..15b924a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -485,9 +485,11 @@
select DRIVERS_GENESYSLOGIC_GL9750
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_INTEL_MIPI_CAMERA
+ select DRIVERS_MTK_WIFI
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
select HAVE_WWAN_POWER_SEQUENCE
select INTEL_GMA_HAVE_VBT
+ select USE_MTCL
config BOARD_GOOGLE_YAVILLA
select BOARD_GOOGLE_BASEBOARD_NISSA
--
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Gerrit-Change-Number: 80305
Gerrit-PatchSet: 5
Gerrit-Owner: David Ruth <druth(a)chromium.org>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80319?usp=email )
Change subject: commonlib: Change GCD function to always use 64 bits
......................................................................
commonlib: Change GCD function to always use 64 bits
It seems that we have some applications where we need to calculate a GCD
in 64 bits. Now, we could instantiate the algorithm multiple times for
different bit width combinations to be able to use the most efficient
one for each problem... but considering that the function usually only
gets called once per callsite per stage, and that software emulation of
64-bit division on 32-bit systems doesn't take *that* long either, we
would probably usually be paying more time loading the second instance
of the function than we save with faster divisions. So let's just make
things easy and always do it in 64-bit and then nobody has to spend time
thinking on which version to call.
Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80319
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Yidi Lin <yidilin(a)google.com>
---
M payloads/libpayload/libc/getopt_long.c
M payloads/libpayload/libc/time.c
M src/arch/arm64/arch_timer.c
M src/commonlib/bsd/gcd.c
M src/commonlib/bsd/include/commonlib/bsd/gcd.h
M src/drivers/analogix/anx7625/anx7625.c
M src/northbridge/intel/ironlake/quickpath.c
M src/soc/rockchip/rk3288/clock.c
M src/soc/rockchip/rk3399/clock.c
M tests/commonlib/bsd/gcd-test.c
10 files changed, 28 insertions(+), 23 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Yidi Lin: Looks good to me, approved
diff --git a/payloads/libpayload/libc/getopt_long.c b/payloads/libpayload/libc/getopt_long.c
index 822ce96..c0303cf 100644
--- a/payloads/libpayload/libc/getopt_long.c
+++ b/payloads/libpayload/libc/getopt_long.c
@@ -122,7 +122,7 @@
*/
nnonopts = panonopt_end - panonopt_start;
nopts = opt_end - panonopt_end;
- ncycle = gcd32(nnonopts, nopts);
+ ncycle = gcd(nnonopts, nopts);
cyclelen = (opt_end - panonopt_start) / ncycle;
for (i = 0; i < ncycle; i++) {
diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
index c38dbfd..28f2b3e 100644
--- a/payloads/libpayload/libc/time.c
+++ b/payloads/libpayload/libc/time.c
@@ -182,7 +182,7 @@
"must be at least 1MHz.\n", hz);
halt();
}
- div = gcd32(hz, mult);
+ div = gcd(hz, mult);
hz /= div;
mult /= div;
}
diff --git a/src/arch/arm64/arch_timer.c b/src/arch/arm64/arch_timer.c
index 3eb5656..742b82c 100644
--- a/src/arch/arm64/arch_timer.c
+++ b/src/arch/arm64/arch_timer.c
@@ -19,7 +19,7 @@
if (tfreq == 0) {
tfreq = raw_read_cntfrq_el0();
mult = USECS_PER_SEC;
- div = gcd32(tfreq, mult);
+ div = gcd(tfreq, mult);
tfreq /= div;
mult /= div;
}
diff --git a/src/commonlib/bsd/gcd.c b/src/commonlib/bsd/gcd.c
index 92b601e..fbc8103 100644
--- a/src/commonlib/bsd/gcd.c
+++ b/src/commonlib/bsd/gcd.c
@@ -4,9 +4,9 @@
#include <commonlib/bsd/helpers.h>
#include <stdint.h>
-uint32_t gcd32(uint32_t a, uint32_t b)
+uint64_t gcd(uint64_t a, uint64_t b)
{
- uint32_t c;
+ uint64_t c;
if (a == 0 || b == 0)
return MAX(a, b);
diff --git a/src/commonlib/bsd/include/commonlib/bsd/gcd.h b/src/commonlib/bsd/include/commonlib/bsd/gcd.h
index 20949de..de02eb5 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/gcd.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/gcd.h
@@ -5,6 +5,6 @@
#include <stdint.h>
-uint32_t gcd32(uint32_t a, uint32_t b);
+uint64_t gcd(uint64_t a, uint64_t b);
#endif /* _COMMONLIB_BSD_GCD_H_ */
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c
index 8726ac0..4792d07 100644
--- a/src/drivers/analogix/anx7625/anx7625.c
+++ b/src/drivers/analogix/anx7625/anx7625.c
@@ -160,7 +160,7 @@
u32 a = *_a, b = *_b, old_a, old_b;
u32 denom = 1;
- gcd_num = gcd32(a, b);
+ gcd_num = gcd(a, b);
a /= gcd_num;
b /= gcd_num;
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index eb79347..aac852a 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -19,7 +19,7 @@
static u32 lcm(u32 a, u32 b)
{
- return (a * b) / gcd32(a, b);
+ return (a * b) / gcd(a, b);
}
struct stru1 {
@@ -49,7 +49,7 @@
int freq_max_reduced;
int freq3, freq4;
- g = gcd32(freq1, freq2);
+ g = gcd(freq1, freq2);
freq1_reduced = freq1 / g;
freq2_reduced = freq2 / g;
freq_min_reduced = MIN(freq1_reduced, freq2_reduced);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index d52fa2a..5b1350a 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -453,7 +453,7 @@
1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
/* set frac divider */
- v = gcd32(GPLL_HZ, hz);
+ v = gcd(GPLL_HZ, hz);
n = (GPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == GPLL_HZ / n * d);
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index fbff5a7..115d289 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -796,7 +796,7 @@
RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3));
/* set frac divider */
- v = gcd32(CPLL_HZ, hz);
+ v = gcd(CPLL_HZ, hz);
n = (CPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == (u64)CPLL_HZ * d / n);
diff --git a/tests/commonlib/bsd/gcd-test.c b/tests/commonlib/bsd/gcd-test.c
index 13fad86..852a3fd 100644
--- a/tests/commonlib/bsd/gcd-test.c
+++ b/tests/commonlib/bsd/gcd-test.c
@@ -3,24 +3,29 @@
#include <commonlib/bsd/gcd.h>
#include <tests/test.h>
-static void test_gcd32(void **state)
+static void test_gcd(void **state)
{
- assert_int_equal(gcd32(17, 11), 1);
- assert_int_equal(gcd32(64, 36), 4);
- assert_int_equal(gcd32(90, 123), 3);
- assert_int_equal(gcd32(65536, 339584), 128);
- assert_int_equal(gcd32(1, 1), 1);
- assert_int_equal(gcd32(1, 123), 1);
- assert_int_equal(gcd32(123, 1), 1);
- assert_int_equal(gcd32(1, UINT32_MAX), 1);
- assert_int_equal(gcd32(UINT32_MAX, 1), 1);
- assert_int_equal(gcd32(UINT32_MAX, UINT32_MAX), UINT32_MAX);
+ assert_int_equal(gcd(17, 11), 1);
+ assert_int_equal(gcd(64, 36), 4);
+ assert_int_equal(gcd(90, 123), 3);
+ assert_int_equal(gcd(65536, 339584), 128);
+ assert_int_equal(gcd(1, 1), 1);
+ assert_int_equal(gcd(1, 123), 1);
+ assert_int_equal(gcd(123, 1), 1);
+ assert_int_equal(gcd(1, UINT32_MAX), 1);
+ assert_int_equal(gcd(UINT32_MAX, 1), 1);
+ assert_int_equal(gcd(UINT32_MAX, UINT32_MAX), UINT32_MAX);
+ assert_int_equal(gcd(1, UINT64_MAX), 1);
+ assert_int_equal(gcd(UINT64_MAX, 1), 1);
+ assert_int_equal(gcd(UINT64_MAX, UINT64_MAX), UINT64_MAX);
+ assert_int_equal(gcd((uint64_t)UINT32_MAX + 1, UINT64_MAX / 2 + 1),
+ (uint64_t)UINT32_MAX + 1);
}
int main(void)
{
const struct CMUnitTest tests[] = {
- cmocka_unit_test(test_gcd32),
+ cmocka_unit_test(test_gcd),
};
return cb_run_group_tests(tests, NULL, NULL);
--
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Change subject: cpu/qemu-x86/cache_as_ram: Move guard
......................................................................
cpu/qemu-x86/cache_as_ram: Move guard
Although entry64.inc does guard against ENV_X86_64, it's more aesthetic
to have it with the other 64bit code below a guard just like other
platforms.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: If3ef19dd6654cd2fa0be3c68dee4a472e7a7935d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80354
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Felix Held: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 0943e35..859b760 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -77,11 +77,11 @@
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
+#if ENV_X86_64
/* entry64.inc preserves ebx. */
#include <cpu/x86/64bit/entry64.inc>
/* Restore the BIST result and timestamps. */
-#if ENV_X86_64
movd %mm2, %rdi
shlq $32, %rdi
movd %mm1, %rsi
--
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Gerrit-Change-Number: 80354
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Change subject: arch/io.h: Add stubs for x86 I/O port functions to other arches
......................................................................
Patch Set 3:
(1 comment)
File src/arch/arm/include/armv7/arch/io.h:
https://review.coreboot.org/c/coreboot/+/80372/comment/7dc29d6b_18ce413d :
PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__);
> Can we just make these all `die()` if you know that they will never get hit anyway? That would make […]
Good point. This might even be a case for dead_code()? Or no implementation
at all if we want it to be a linker error.
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