coreboot-gerrit February 2024

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[L] Change in coreboot[main]: arch/io.h: Add stubs for x86 I/O port functions to other arches
by Julius Werner (Code Review) 08 Feb '24

08 Feb '24

Attention is currently required from: Alper Nebi Yasak, Nico Huber, Philipp Hug, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add stubs for x86 I/O port functions to other arches ...................................................................... Patch Set 3: (1 comment) File src/arch/arm/include/armv7/arch/io.h: https://review.coreboot.org/c/coreboot/+/80372/comment/e0b15e5a_2e37c2c1 : PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__); > Well, the way the QEMU drivers are written right now that wouldn't work, since due to the way the de […] (Or just no implementation at all, yeah, that's probably an even clearer error message in this specific case.) -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Feb 2024 21:33:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/io.h: Add stubs for x86 I/O port functions to other arches
by Julius Werner (Code Review) 08 Feb '24

08 Feb '24

Attention is currently required from: Alper Nebi Yasak, Nico Huber, Philipp Hug, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add stubs for x86 I/O port functions to other arches ...................................................................... Patch Set 3: (1 comment) File src/arch/arm/include/armv7/arch/io.h: https://review.coreboot.org/c/coreboot/+/80372/comment/8f3fd526_fc1790d0 : PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__); > Good point. This might even be a case for dead_code()? Or no implementation […] Well, the way the QEMU drivers are written right now that wouldn't work, since due to the way the decision is made from a flag set in `struct resource` the compiler won't be able to eliminate it. But we could replace all the open-coded `res->flags & RESOURCE_IO` checks with a static inline helper function `resource_is_io(res)` which would just always return false for non-x86. Then we could define all the I/O accesors as macros that just evaluate to `dead_code()` in Arm headers. That's probably the best option. -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 3 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Feb 2024 21:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/device: fix soft_reserved_ram_resource macro
by Felix Held (Code Review) 08 Feb '24

08 Feb '24

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80409?usp=email ) Change subject: include/device/device: fix soft_reserved_ram_resource macro ...................................................................... Patch Set 2: (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/80409/comment/93eb372b_1082bf18 : PS2, Line 386: soft_reserved_ram_resource > Can we keep it consistent and use _kb or change the actual users of this to use byte sized values? oh, wait, the suffix is missing there too in general, i'd like to revive Kyosti's work to get rid of the resource functions taking kilobytes as arguments, but haven't gotten around to do or look into that -- To view, visit https://review.coreboot.org/c/coreboot/+/80409?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Gerrit-Change-Number: 80409 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 08 Feb 2024 21:29:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/data_fabric/domain: drop unneeded parenthesis
by Felix Held (Code Review) 08 Feb '24

08 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80408?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/common/data_fabric/domain: drop unneeded parenthesis ...................................................................... soc/amd/common/data_fabric/domain: drop unneeded parenthesis Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I84a7b7b1b2c45b773c6f10b39e7813db3f96546e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80408 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/data_fabric/domain.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index afe79fe..ab85e2b5 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -279,7 +279,7 @@ continue; /* Don't add MMIO producer ranges for reserved MMIO regions from non-PCI devices */ - if ((res->flags & IORESOURCE_RESERVE)) + if (res->flags & IORESOURCE_RESERVE) continue; /* Don't add MMIO producer ranges for DRAM regions */ if (res->flags & IORESOURCE_STORED) -- To view, visit https://review.coreboot.org/c/coreboot/+/80408?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a7b7b1b2c45b773c6f10b39e7813db3f96546e Gerrit-Change-Number: 80408 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/common/data_fabric/domain: don't report DRAM as MMIO producer
by Felix Held (Code Review) 08 Feb '24

08 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80407?usp=email ) Change subject: soc/amd/common/data_fabric/domain: don't report DRAM as MMIO producer ...................................................................... soc/amd/common/data_fabric/domain: don't report DRAM as MMIO producer In commit 30f36c35e75a ("soc/amd: rework DRAM and fixed resource reporting") the reporting of the DRAM resources was moved from the northbridge PCI device to the domain device. amd_pci_domain_fill_ssdt didn't skip those DRAM resources when generation the resource producer ranges which made Windows 10 very unhappy when it tried to evaluating the ACPI tables causing it to reboot in a loop. To fix this, add a check to also skip the resources that have the IORESOURCE_STORED flag set when generating the resource producer ranges for the PCI root. TEST=Windows 10 now successfully boots and reboots again on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b6d3fd8c7f89aa4364de7963d745aef8d6b6f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80407 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/data_fabric/domain.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index f5d7216..afe79fe 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -281,6 +281,9 @@ devices */ if ((res->flags & IORESOURCE_RESERVE)) continue; + /* Don't add MMIO producer ranges for DRAM regions */ + if (res->flags & IORESOURCE_STORED) + continue; switch (res->flags & IORESOURCE_TYPE_MASK) { case IORESOURCE_IO: write_ssdt_domain_io_producer_range(acpi_device_name(domain), -- To view, visit https://review.coreboot.org/c/coreboot/+/80407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b6d3fd8c7f89aa4364de7963d745aef8d6b6f42 Gerrit-Change-Number: 80407 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: libpayload: timer: Revert timer_hz() return type to 64-bits
by Julius Werner (Code Review) 08 Feb '24

08 Feb '24

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80320?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: libpayload: timer: Revert timer_hz() return type to 64-bits ...................................................................... libpayload: timer: Revert timer_hz() return type to 64-bits It seems that reducing the return type of timer_hz() to uint32_t in CB:78888 was a bad idea... some Intel platforms actually use their raw CPU clock for the timestamp counter which can be higher than 4GHz. This patch reverts it back to uint64_t. Also remove the redundant assertion in timer/generic.c since timer_us() itself already does that check. Cq-Depend: chromium:5274555 Change-Id: I471c7de7a28aec5bb965b23525ed579481ac8361 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M payloads/libpayload/drivers/timer/arm64_arch_timer.c M payloads/libpayload/drivers/timer/generic.c M payloads/libpayload/drivers/timer/rdtsc.c M payloads/libpayload/include/libpayload.h M payloads/libpayload/libc/time.c 5 files changed, 8 insertions(+), 10 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/payloads/libpayload/drivers/timer/arm64_arch_timer.c b/payloads/libpayload/drivers/timer/arm64_arch_timer.c index b4d2b86..087d9e7 100644 --- a/payloads/libpayload/drivers/timer/arm64_arch_timer.c +++ b/payloads/libpayload/drivers/timer/arm64_arch_timer.c @@ -32,7 +32,7 @@ #include <arch/lib_helpers.h> #include <libpayload.h> -uint32_t timer_hz(void) +uint64_t timer_hz(void) { return raw_read_cntfrq_el0(); } diff --git a/payloads/libpayload/drivers/timer/generic.c b/payloads/libpayload/drivers/timer/generic.c index bd5674b..46bc291 100644 --- a/payloads/libpayload/drivers/timer/generic.c +++ b/payloads/libpayload/drivers/timer/generic.c @@ -33,10 +33,8 @@ #include <assert.h> #include <libpayload.h> -uint32_t timer_hz(void) +uint64_t timer_hz(void) { - /* libc/time.c currently requires all timers to be at least 1MHz. */ - assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000); return CONFIG_LP_TIMER_GENERIC_HZ; } diff --git a/payloads/libpayload/drivers/timer/rdtsc.c b/payloads/libpayload/drivers/timer/rdtsc.c index 952bc0b..d5bf1d2 100644 --- a/payloads/libpayload/drivers/timer/rdtsc.c +++ b/payloads/libpayload/drivers/timer/rdtsc.c @@ -35,10 +35,9 @@ #include <arch/rdtsc.h> #include <assert.h> -uint32_t timer_hz(void) +uint64_t timer_hz(void) { - assert(UINT32_MAX / 1000 >= lib_sysinfo.cpu_khz); - return lib_sysinfo.cpu_khz * 1000; + return (uint64_t)lib_sysinfo.cpu_khz * 1000; } uint64_t timer_raw_value(void) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 6da4564..5e34124 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -519,7 +519,7 @@ /* Timer functions. */ /* Defined by each architecture. */ -uint32_t timer_hz(void); +uint64_t timer_hz(void); uint64_t timer_raw_value(void); uint64_t timer_us(uint64_t base); /* Generic. */ diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 28f2b3e..64de800 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -171,14 +171,15 @@ u64 timer_us(u64 base) { - static u32 hz, mult = USECS_PER_SEC; + static u64 hz; + static u32 mult = USECS_PER_SEC; u32 div; // Only check timer_hz once. Assume it doesn't change. if (hz == 0) { hz = timer_hz(); if (hz < mult) { - printf("Timer frequency %" PRIu32 " is too low, " + printf("Timer frequency %" PRIu64 " is too low, " "must be at least 1MHz.\n", hz); halt(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I471c7de7a28aec5bb965b23525ed579481ac8361 Gerrit-Change-Number: 80320 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: libpayload: timer: Revert timer_hz() return type to 64-bits
by Julius Werner (Code Review) 08 Feb '24

08 Feb '24

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80320?usp=email ) Change subject: libpayload: timer: Revert timer_hz() return type to 64-bits ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80320/comment/f3880484_b09e03b2 : PS1, Line 16: > Cq-Depend: chromium:5274555 Done Patchset: PS1: > We also need to revert http://crrev. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I471c7de7a28aec5bb965b23525ed579481ac8361 Gerrit-Change-Number: 80320 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Feb 2024 21:06:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
by Jason Nein (Code Review) 08 Feb '24

08 Feb '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Matt DeVillier, Tim Van Patten. Jason Nein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80237?usp=email ) Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2 ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80237/comment/a8f58489_9816c41c : PS1, Line 12: TEST=test pass over 10k cycles > Please also measure the power impact of this change. You can use the following CL as an example: […] we're working on it Patchset: PS1: > As noted by the build bot, please use the `main` branch. done -- To view, visit https://review.coreboot.org/c/coreboot/+/80237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Gerrit-Change-Number: 80237 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Feb 2024 20:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/up/squared: Make mini PCIe port mode configurable
by Nico Huber (Code Review) 08 Feb '24

08 Feb '24

Attention is currently required from: Felix Singer, Reto Buerki. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80261?usp=email ) Change subject: mb/up/squared: Make mini PCIe port mode configurable ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80261/comment/0b5f073f_2874862e : PS2, Line 9: Add ENABLE_MSATA config knob and pad configuration to put Mini PCIe port : into mSATA mode. > I think we should figure out if PCIe still works, so that we don't create confusion. […] I've checked pinouts of mini PCIe and mSATA, they use the same pins for their lanes. And as Apollo Lake has these on separate pins, there is no other reasonable way to hook this up than a separate muxer. So it seems 99% sure that PCIe doesn't work with SATA enabled and vice versa, and I don't see why one would expect otherwise. Making it a choice in Kconfig seems right to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/80261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Gerrit-Change-Number: 80261 Gerrit-PatchSet: 2 Gerrit-Owner: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Thu, 08 Feb 2024 20:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: tree; Remove unused <lib.h>
by Elyes Haouas (Code Review) 08 Feb '24

08 Feb '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80433?usp=email ) Change subject: tree; Remove unused <lib.h> ...................................................................... tree; Remove unused <lib.h> Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/efi/efivars.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/spi/issi.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/80433/1 diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c index 9a3233f..e7eabf4 100644 --- a/src/drivers/efi/efivars.c +++ b/src/drivers/efi/efivars.c @@ -9,7 +9,6 @@ #include <vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h> #include <vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiFirmwareVolume.h> #include <vendorcode/intel/edk2/UDK2017/MdeModulePkg/Include/Guid/VariableFormat.h> -#include <lib.h> #include "efivars.h" diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 894f9cc..2aec5db 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -8,7 +8,6 @@ #include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> -#include <lib.h> #include <string.h> #include <timestamp.h> diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 200c89a..5c40966 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -6,7 +6,6 @@ #include <fsp/ramstage.h> #include <fsp/util.h> #include <framebuffer_info.h> -#include <lib.h> #include <stage_cache.h> #include <string.h> #include <timestamp.h> diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index 5ccec59..a43364a 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <fsp/api.h> #include <fsp/fsp_gop_blt.h> -#include <lib.h> #include <stdlib.h> static bool is_bmp_image_valid(efi_bmp_image_header *header) diff --git a/src/drivers/intel/fsp2_0/fsp_timestamp.c b/src/drivers/intel/fsp2_0/fsp_timestamp.c index 4e50f85..872cf91 100644 --- a/src/drivers/intel/fsp2_0/fsp_timestamp.c +++ b/src/drivers/intel/fsp2_0/fsp_timestamp.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <fsp/util.h> -#include <lib.h> #define TIMESTAMP_TO_MICRO(x) ((x) / 1000ull) diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c index 45fe5a1..d2000b9 100644 --- a/src/drivers/spi/issi.c +++ b/src/drivers/spi/issi.c @@ -5,7 +5,6 @@ #include <spi_flash.h> #include <spi-generic.h> #include <delay.h> -#include <lib.h> #include "spi_flash_internal.h" diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b318be0..bc5439d 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -13,7 +13,6 @@ #include <device/pci_ids.h> #include <string.h> #include <stdlib.h> -#include <lib.h> #include <cpu/x86/mp.h> #include <Porting.h> #include <Topology.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index ab7f04b..eebb122 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -4,7 +4,6 @@ #include <delay.h> #include <device/mmio.h> #include <edid.h> -#include <lib.h> #include <soc/clock.h> #include <soc/display/edp_reg.h> #include <soc/display/edp_phy.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/80433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Gerrit-Change-Number: 80433 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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