Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80570?usp=email )
Change subject: mb/google/rex/variants/deku: remove IOEX, replace with GPIOs
......................................................................
mb/google/rex/variants/deku: remove IOEX, replace with GPIOs
Make the required change as per the details in the bug.
BUG=b:325533052
TEST=Built FW image correctly.
Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/mainboard/google/rex/variants/deku/gpio.c
1 file changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80570/1
diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c
index 2e44620..6158fc8 100644
--- a/src/mainboard/google/rex/variants/deku/gpio.c
+++ b/src/mainboard/google/rex/variants/deku/gpio.c
@@ -59,8 +59,8 @@
PAD_NC(GPP_B05, NONE),
/* GPP_B06 : net NC is not present in the given design */
PAD_NC(GPP_B06, NONE),
- /* GPP_B07 : IOEX_INT_ODL */
- PAD_CFG_GPI(GPP_B07, NONE, DEEP),
+ /* GPP_B07 : net NC is not present in the given design */
+ PAD_NC(GPP_B07, NONE),
/* GPP_B08 : [] ==> PWM_BUZZER */
PAD_CFG_GPO(GPP_B08, 0, DEEP),
/* GPP_B09 : net NC is not present in the given design */
@@ -251,22 +251,22 @@
PAD_NC(GPP_F09, NONE),
/* GPP_F10 : net NC is not present in the given design */
PAD_NC(GPP_F10, NONE),
- /* GPP_F11 : net NC is not present in the given design */
- PAD_NC(GPP_F11, NONE),
- /* GPP_F12 : net NC is not present in the given design */
- PAD_NC(GPP_F12, NONE),
- /* GPP_F13 : net NC is not present in the given design */
- PAD_NC(GPP_F13, NONE),
- /* GPP_F14 : net NC is not present in the given design */
- PAD_NC(GPP_F14, NONE),
- /* GPP_F15 : net NC is not present in the given design */
- PAD_NC(GPP_F15, NONE),
- /* GPP_F16 : net NC is not present in the given design */
- PAD_NC(GPP_F16, NONE),
- /* GPP_F17 : net NC is not present in the given design */
- PAD_NC(GPP_F17, NONE),
- /* GPP_F18 : net NC is not present in the given design */
- PAD_NC(GPP_F18, NONE),
+ /* GPP_F11 : [] ==> AV_GPIO_P0 */
+ PAD_CFG_GPO(GPP_F11, 0, DEEP),
+ /* GPP_F12 : [] ==> AV_GPIO_P1 */
+ PAD_CFG_GPO(GPP_F12, 0, DEEP),
+ /* GPP_F13 : [] ==> AV_GPIO_P2 */
+ PAD_CFG_GPO(GPP_F13, 0, DEEP),
+ /* GPP_F14 : [] ==> AV_GPIO_P3 */
+ PAD_CFG_GPO(GPP_F14, 0, DEEP),
+ /* GPP_F15 : [] ==> AV_GPIO_P4 */
+ PAD_CFG_GPO(GPP_F15, 0, DEEP),
+ /* GPP_F16 : [] ==> AV_GPIO_P5 */
+ PAD_CFG_GPO(GPP_F16, 0, DEEP),
+ /* GPP_F17 : [] ==> AV_GPIO_P6 */
+ PAD_CFG_GPO(GPP_F17, 0, DEEP),
+ /* GPP_F18 : [] ==> AV_GPIO_P7 */
+ PAD_CFG_GPO(GPP_F18, 0, DEEP),
/* GPP_F19 : [GPP_F19_STRAP] ==> Component NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20 : [GPP_F20_STRAP] ==> Component NC */
@@ -275,7 +275,7 @@
PAD_NC(GPP_F21, NONE),
/* GPP_F22 : [] ==> GPP_F22_ISH_GP8A */
PAD_NC(GPP_F22, NONE),
- /* GPP_F23 : [] ==> TP_SOC_ISH_MCF_INT_L */
+ /* GPP_F23 : [] ==> GPP_F23_ISH_GP9A */
PAD_NC(GPP_F23, NONE),
/* GPP_H00 : GPP_H00_STRAP ==> Component NC */
@@ -310,10 +310,10 @@
PAD_NC(GPP_H16, NONE),
/* GPP_H17 : net NC is not present in the given design */
PAD_NC(GPP_H17, NONE),
- /* GPP_H19 : [] ==> I2C_IOEX_SDA */
- PAD_CFG_NF_LOCK(GPP_H19, NONE, NF1, LOCK_CONFIG),
- /* GPP_H20 : [] ==> I2C_IOEX_SCL */
- PAD_CFG_NF_LOCK(GPP_H20, NONE, NF1, LOCK_CONFIG),
+ /* GPP_H19 : net NC is not present in the given design */
+ PAD_NC(GPP_H19, NONE),
+ /* GPP_H20 : net NC is not present in the given design */
+ PAD_NC(GPP_H20, NONE),
/* GPP_H21 : net NC is not present in the given design */
PAD_NC(GPP_H21, NONE),
/* GPP_H22 : net NC is not present in the given design */
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257
Gerrit-Change-Number: 80570
Gerrit-PatchSet: 1
Gerrit-Owner: Eran Mitrani <mitrani(a)google.com>
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Attention is currently required from: Aryan Arora, Paul Menzel, Simon Glass.
Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80185?usp=email )
Change subject: device/oprom/include/x86emu/regs.h: Refactor code to match coding style standards
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80185/comment/ebd49e93_c8b88528 :
PS1, Line 6:
> If it helps, the comments are confusing as they refer to the line below. […]
Maybe "dev/oprom/inc/x86emu/regs.h: Refactor to match coding style"
https://review.coreboot.org/c/coreboot/+/80185/comment/5dfd533a_fcb75f60 :
PS1, Line 6:
> > `A patch subject line should describe the change not the tool that found it` […]
I'm not sure what tool this is referring to. I think this complaint is incorrect.
Commit Message:
https://review.coreboot.org/c/coreboot/+/80185/comment/3d0569d4_2c4f25cb :
PS2, Line 9: and
Move this "and" to the following line.
Patchset:
PS2:
Hi, It looks like you haven't contributed to the coreboot project before.
Welcome and thank you for the patch. We hope that this is just the first of many.
Please let us know if there's anything we can do to help get your first sets patches merged as you get used to the contribution process.
The coreboot project has a hands-off policy regarding other people's patches so nobody here is going to update the contents without your permission. If you would you like someone to take over your patches at any point, please just post a comment to that effect on the specific patch.
You might find the coding style guide and the gerrit guidelines useful to read.
https://doc.coreboot.org/contributing/coding_style.htmlhttps://doc.coreboot.org/contributing/gerrit_guidelines.html
If you want to talk with anyone, you can talk to developers on one of the many options we have:
https://doc.coreboot.org/community/forums.html
Again, please let us know if you have any questions, or if there's anything we can do to help.
I'm marking this as a +2 since the patch itself looks good, there's just an issue with the commit message.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80453?usp=email )
Change subject: drivers/crb: Check for PTT before attempting to initialize CRB TPM
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80453/comment/c37854ee_1b6d7a76 :
PS1, Line 9: We can assume that platforms, which select HAVE_INTEL_PTT, will not
: have any other CRB TPM than PTT.
> Probably the dTPM could use CRB interface if it supports CRB besides FIFO. […]
Now I see this assumption is already in the code, you just made the function return sooner if PTT is off. I initially thought this changed behaviour to ignore some TPMs which weren't ignored before.
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80553?usp=email )
Change subject: soc/intel/common/block/dtt: Add ACPI stub for TCPU device
......................................................................
Patch Set 3:
This change is ready for review.
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Gerrit-Change-Number: 80553
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80557?usp=email )
Change subject: mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTT
......................................................................
mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTT
It's already selected at the SoC level, so selecting at the board
level is redundant.
Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/intel/tglrvp/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/80557/1
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index b8110dd..b6f0187 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -14,7 +14,6 @@
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select SOC_INTEL_TIGERLAKE
- select SOC_INTEL_COMMON_BLOCK_DTT
select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_INTEL_ISH
select EC_ACPI
--
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