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Change subject: soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devices
......................................................................
soc/intel/common/tcss: Rename tcss_mux_init to disconnect_tcss_devices
Rename tcss_mux_init to disconnect_tcss_devices to make it clear
what this function is doing, as it doesn't initialise anything.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584
---
M src/soc/intel/common/block/tcss/tcss.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/79874/7
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Change subject: mb/starlabs/starbook: Always include the tcss.asl
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/starlabs/starbook/{kbl,cml}: Remove libgfxinit code
......................................................................
Patch Set 3: Code-Review+2
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Hello build bot (Jenkins),
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Change subject: mb/starlabs/starbook/{kbl,cml}: Remove libgfxinit code
......................................................................
mb/starlabs/starbook/{kbl,cml}: Remove libgfxinit code
libgfxinit isn't used in any build, nor does it work with GRUB on
these boards, so remove it.
Change-Id: I86af51f07f29971070bdccc3a589e807425cb83a
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starbook/Kconfig
M src/mainboard/starlabs/starbook/Makefile.mk
M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
D src/mainboard/starlabs/starbook/variants/cml/gma-mainboard.ads
M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
D src/mainboard/starlabs/starbook/variants/kbl/gma-mainboard.ads
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
8 files changed, 0 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/80462/3
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Change subject: mb/starlabs/starbook: Always include the tcss.asl
......................................................................
mb/starlabs/starbook: Always include the tcss.asl
The tcss.asl doesn't just relate to tcss, it is required for core
scheduling, so include it for all platforms.
Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starbook/dsdt.asl
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/80485/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80567?usp=email )
Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
This patch optimizes boot time by avoiding redundant microcode updates
from RW CBFS when the RO descriptor is locked, indicating a fixed RO
image.
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates without affecting
AP FW boot time.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS
microcode loading when RO is locked.
Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/cpu.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/80567/1
diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
index 54217ea5..e990ae3 100644
--- a/src/soc/intel/meteorlake/cpu.c
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/common/common.h>
+#include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/lapic.h>
@@ -214,3 +215,24 @@
/* Thermal throttle activation offset */
configure_tcc_thermal_target();
}
+
+int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
+{
+ if (!CONFIG(CHROMEOS))
+ return 0;
+ /*
+ * Locked RO Descriptor Implications:
+ *
+ * - A locked descriptor signals the RO binary is fixed; the FIT will load the
+ * RO's microcode during system reset.
+ * - Attempts to load newer microcode from the RW CBFS will cause a boot-time
+ * delay (~60ms, core-dependent), as the microcode must be reloaded on BSP+APs.
+ * - The kernel can load microcode updates without impacting AP FW boot time.
+ * - Skipping RW CBFS microcode loading is low-risk when the RO is locked,
+ * prioritizing fast boot times.
+ */
+ if (CONFIG(LOCK_MANAGEMENT_ENGINE) && current_patch_id)
+ return 1;
+
+ return 0;
+}
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Change subject: device/device_const: add pcidev_path_on_segbus
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> @Patrick with CB:80093 and following, i can abandon this patch, right?
Yes, please abandon.
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Change subject: device/device_const: add pcidev_path_on_segbus
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
@Patrick with CB:80093 and following, i can abandon this patch, right?
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80455?usp=email )
Change subject: drivers/pc80/tpm: Disable device if TPM not present
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/80455/comment/8a9d90ed_b263601e :
PS1, Line 898: (
> Done
Acknowledged
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